SI5341D-D15742-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5341D-D15742-GMR is a factory pre-programmed, ultra-low jitter clock generator featuring 10 outputs and fractional synthesis. It supports any-frequency input to any-frequency output within a maximum differential frequency of 350 MHz. The device operates on a 1.8 V core supply and 3.3 V I/O supply, housed in a 64-QFN package. It delivers 90 fs rms phase jitter and includes an internal PLL with MultiSynth technology.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using fractional synthesizer technology
• Provides highly configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL signal formats
• Features glitchless on-the-fly output frequency changes via Digitally Controlled Oscillator (DCO) modes
• Supports in-circuit programming with non-volatile OTP memory for custom factory pre-programming

Clock Generators, PLLs, Frequency Synthesizers Applications

• Clock tree generation replacing XOs, buffers, and signal format translators
• Clocking for FPGAs, processors, and memory systems
• Ethernet switches and routers
• OTN framers, mappers, and processors
• Test equipment and instrumentation

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific configuration sequence '15742' against the official ClockBuilder Pro data sheet addendum to ensure the pre-programmed register settings match your design requirements. Confirm that the GMR suffix indicates tape and reel packaging suitable for automated assembly processes.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when a fixed, factory-defined clock configuration is required without serial interface programming during operation. Ensure the 350 MHz maximum output frequency meets system needs, as higher performance grades like Si5341A support up to 1028 MHz. Verify compatibility with available input sources such as crystals or differential clocks.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5341/40 Rev D family, which combines a wide-band PLL with proprietary MultiSynth technology. The Si5341 variant specifically provides four inputs and ten outputs in a 64-pin QFN package, designed to replace multiple discrete clock components with a single integrated solution.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5341B-Dxxxxx-GMR: Offers identical specifications but requires different factory pre-programming sequences.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How is the device configured if it is factory pre-programmed?

The device is programmed at the factory using ClockBuilder Pro software. Custom part numbers are assigned automatically based on the desired configuration, allowing the device to generate specific clock frequencies immediately upon power-up.

What is the purpose of the Zero Delay Mode?

Zero delay mode cancels out internal delays by feeding an output back to the FB_IN pins externally. This ensures a fixed and consistent minimum delay between the selected input and outputs, which is critical for specific timing applications.

Can the output drivers be disabled individually?

Yes, outputs can be individually disabled through register control. They can also be globally enabled or disabled via the OEb pin, with options for synchronous or asynchronous disable states to prevent runt pulses.