SI5345A-B05668-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5345A-B05668-GM is a low-jitter, 10-output clock multiplier and jitter attenuator from the Si5345 Rev D family. It supports any-frequency generation up to 1028 MHz using integer and fractional synthesis modes. The device features four inputs (differential or LVCMOS) and ten configurable outputs compatible with LVDS, LVPECL, LVCMOS, CML, and HCSL. It operates on a 1.71 V to 3.47 V supply within a -40 °C to +85 °C temperature range. The component utilizes fourth-generation DSPLL technology for ultra-low jitter performance of 90 fs rms.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Combines fourth-generation DSPLL and MultiSynth technologies for high-performance jitter attenuation and frequency multiplication.
• Supports free-run, synchronous, and holdover modes with automatic or manual input clock switching capabilities.
• Features fully integrated loop filter and digitally programmable jitter attenuation bandwidth for optimized application-level performance.
• Includes in-circuit programmable non-volatile memory to ensure known frequency configuration upon power-up.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm factory preprogramming details. Confirm package availability and lead times through authorized distributors. Ensure compliance with RoHS-6 standards and check for any recent process change notifications that may affect specifications.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when applications require up to 10 output clocks with frequencies up to 1028 MHz. It is suitable for designs needing integer and fractional synthesis modes. Verify that the required input frequency range fits within the differential (8 kHz–750 MHz) or LVCMOS (8 kHz–250 MHz) limits. Ensure the system design accommodates the 64-QFN 9x9 mm package dimensions.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345 Rev D series, which includes variants like the Si5345A-D-GM and Si5345B-D-GM. The 'A' designation indicates support for output frequencies up to 1028 MHz with both integer and fractional synthesis. The 'D' suffix denotes the Rev D hardware revision. Custom factory preprogrammed devices use a numerical sequence in the part number to represent the specific configuration.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5345A-D-GM

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency supported by the SI5345A variant?

The SI5345A variant supports output frequencies ranging from 100 Hz to 1028 MHz for differential outputs and 100 Hz to 250 MHz for LVCMOS outputs.

How does the device handle input clock switching?

The device supports both automatic and manual input clock switching. Automatic switching uses an internal state machine based on input qualification and priority, while manual switching can be controlled via pins or registers.

What is the purpose of the Fastlock feature?

The Fastlock feature allows the DSPLL to acquire lock faster by using a temporary higher loop bandwidth during the lock acquisition process. Once lock is achieved, it reverts to the normal lower loop bandwidth setting.