SI5345B-B04138-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345B-B04138-GMR is a jitter attenuating clock multiplier from the Si5345 family, featuring four inputs and ten outputs in a 64-QFN package. It utilizes fourth-generation DSPLL and MultiSynth technologies to generate any combination of output frequencies from any input frequency with ultra-low jitter performance of 90 fs rms. The device supports differential input frequencies from 8 kHz to 750 MHz and LVCMOS inputs up to 250 MHz. Output frequencies range from 100 Hz to 350 MHz for differential formats and up to 250 MHz for LVCMOS. It operates within a temperature range of -40°C to +85°C and includes programmable jitter attenuation bandwidth.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using fractional synthesis
• Features ultra-low jitter performance of 90 fs rms with digitally programmable loop bandwidth
• Supports hitless input clock switching between fractionally related clocks
• Includes in-circuit programmable non-volatile memory for known power-up configuration

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific factory preprogrammed configuration associated with the B04138 suffix against the design requirements. Confirm that the QFN-64 package dimensions and pinout match the PCB footprint. Ensure the serial interface settings align with the system controller capabilities.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when ten independent clock outputs are required with strict jitter constraints. The B-series designation indicates a maximum output frequency limit of 350 MHz, suitable for most standard networking and telecom applications. Verify compatibility with the desired output voltage standards such as LVDS, LVPECL, or HCSL.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5345/44/42 Rev D family of jitter attenuators. The Si5345 variant specifically provides four inputs and ten outputs, distinguishing it from the Si5344 (four outputs) and Si5342 (two outputs). All variants share the same core DSPLL and MultiSynth architecture.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

SI5345B-D-GM

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency for the SI5345B series?

The SI5345B series supports output frequencies up to 350 MHz.

Does the device support locking to gapped input clocks?

Yes, the DSPLL supports locking to input clocks with missing periods, provided the minimum frequency is 10 MHz with no more than two missing cycles out of every eight.

How is the jitter attenuation bandwidth controlled?

The jitter attenuation bandwidth is digitally programmable via the serial interface, ranging from 0.1 Hz to 4 kHz.