SI5345B-D06675-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5345B-D06675-GMR is a clock synthesizer and jitter cleaner from Skyworks Solutions, belonging to the Si5345 family. It features 10 outputs with a maximum output frequency of 350 MHz. The device supports CML, HCSL, LVCMOS, LVDS, and LVPECL output levels. Input levels include differential and LVCMOS, with a maximum input frequency of 750 MHz. It operates on a power supply between 1.71 V and 3.47 V. The component is housed in a QFN-64 package and functions within a temperature range of -40 °C to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any combination of output frequencies from any input frequency using fourth-generation DSPLL and MultiSynth technologies.
• Features ultra-low jitter performance of 90 fs rms for high-speed networking applications.
• Supports hitless input clock switching with automatic or manual selection capabilities.
• Includes in-circuit programmable non-volatile memory (NVM) for known frequency configuration at power-up.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN muxponders and transponders
• 10/40/100 G networking line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• SONET/SDH line cards

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to ensure compatibility with required packaging options and factory preprogramming configurations. Confirm that the device meets all relevant environmental compliance standards such as RoHS requirements before finalizing procurement specifications.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when an application requires up to ten output clocks with frequencies capped at 350 MHz. Ensure the design accommodates the QFN-64 package dimensions and thermal requirements. Verify that the input signal types match the supported differential or LVCMOS ranges for optimal jitter attenuation performance.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component is part of the Si5345 series, which utilizes DSPLL and MultiSynth technologies for jitter attenuation. The 'B' designation indicates a maximum output frequency limit of 350 MHz, distinguishing it from higher-frequency variants in the same family. The 'D' suffix denotes the Rev D silicon revision.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Compatible substitutes within the same family include SI5345A-D-GMR and SI5345C-D-GMR, provided the application does not require frequencies exceeding 350 MHz or integer-only synthesis modes respectively.