SI5346B-B05206-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5346B-B05206-GM is a dual DSPLL jitter attenuator from Skyworks Solutions, packaged in a 44-QFN (7x7 mm) form factor. It features four inputs and four outputs, supporting any-frequency conversion with a maximum output frequency of 350 MHz. The device operates on a core voltage of 1.8 V ±5% and an I/O voltage ranging from 1.8 V to 3.3 V. It delivers ultra-low jitter performance, typically 95 fs rms within the 12 kHz to 20 MHz bandwidth range. The component supports differential input frequencies up to 750 MHz and LVCMOS inputs up to 250 MHz. Operating temperatures range from -40 °C to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual independent DSPLLs enable flexible routing of any input clock to any output clock via a programmable crosspoint.
• Supports hitless and glitchless input switching, including automatic selection based on priority and manual control.
• Integrates in-circuit programmable non-volatile memory for persistent configuration storage and known power-up states.
• Provides comprehensive status monitoring for Loss of Signal (LOS), Out of Frequency (OOF), and Loss of Lock (LOL).

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches
• Broadcast video

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm package type and temperature grade. Confirm that the factory pre-programmed configuration ID matches the required timing plan. Check for RoHS compliance status and lead time availability through authorized distributors.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model when a dual-DSPLL architecture with four outputs is sufficient for the design. Ensure the required output frequency does not exceed 350 MHz. Verify compatibility with available input signal types, such as differential or LVCMOS sources. Consider the 44-QFN package size constraints relative to the PCB layout requirements.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5346 family, which serves as the dual-DSPLL counterpart to the quad-DSPLL Si5347 series. Both share similar functional capabilities but differ in pin count and output capacity. The Si5346 utilizes a smaller 44-QFN package compared to the Si5347's 64-QFN, offering a compact solution for space-constrained applications requiring high-performance jitter attenuation.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The Si5346A-D-GM offers a higher maximum output frequency of 720 MHz. The Si5347 series provides four DSPLLs and eight outputs in a larger package. Verify electrical compatibility and pinout differences before substituting.