SI5346B-B06705-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5346B-B06705-GMR is a dual DSPLL jitter attenuator and clock multiplier from Skyworks Solutions. It features two independent DSPLLs, four inputs, and four outputs in a 44-QFN package. The device supports any-frequency conversion with ultra-low jitter of 95 fs rms (12 kHz–20 MHz). Input frequencies range from 8 kHz to 750 MHz (differential) or 250 MHz (LVCMOS), while output frequencies reach up to 720 MHz (differential) or 250 MHz (LVCMOS). Core voltage is 1.8 V ±5%, with independent output supplies of 3.3, 2.5, or 1.8 V. Operating temperature is –40 to +85 °C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Dual independent DSPLLs enable flexible crosspoint routing between any input and any output.
• Supports hitless and glitchless input switching with automatic holdover modes.
• Programmable loop bandwidth allows precise jitter attenuation control.
• Includes status monitoring for loss of signal, out-of-range, and loss of lock.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet
• Carrier Ethernet switches
• Broadcast video

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current datasheet to confirm package type and temperature range. Confirm RoHS compliance status as required by project specifications. Check for availability of factory pre-programmed variants if custom configurations are needed. Ensure serial interface compatibility with existing system controllers.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when dual independent timing paths are required within a compact form factor. The Si5346 is suitable for applications needing high integration and low jitter performance. Consider the Si5347 if eight outputs or quad DSPLLs are necessary. Verify that the required output frequency ranges fit within the differential or LVCMOS limits specified.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5347/46 Rev D family, utilizing fourth-generation DSPLL technology. It serves as the dual-PLL variant of the Si5347, offering similar functionality in a smaller 44-QFN package. The series is designed for high-performance clock generation and jitter cleaning in telecommunications and networking equipment.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Si5346A-Dxxxxx-GMR offers a wider frequency range up to 720 MHz for all outputs. Si5347B-Dxxxxx-GMR provides quad DSPLLs and eight outputs in a larger package. Direct pin-to-pin replacement requires verifying output count and frequency specifications match the design requirements.