SI5347A-B04780-GMR

Clock Generators, PLLs, Frequency Synthesizers Overview

The SI5347A-B04780-GMR is a quad DSPLL jitter attenuator and clock synthesizer from Skyworks Solutions. It features four independent DSPLLs with eight outputs in a 64-QFN package. The device supports any-frequency conversion with an input range of 8 kHz to 750 MHz (differential) or 25–54 MHz (crystal). Output frequencies reach up to 720 MHz (differential) or 250 MHz (LVCMOS). Typical output jitter is 95 fs rms (12 kHz–20 MHz). Core voltage is 1.8 V ±5%, with independent 3.3, 2.5, or 1.8 V output supplies. Operating temperature is -40°C to +85°C.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Four independent DSPLLs enable flexible routing of any input to any output for maximum integration.
• Supports hitless and glitchless input switching with automatic holdover modes for high reliability.
• Programmable via serial interface with non-volatile memory for known power-up configurations.

Clock Generators, PLLs, Frequency Synthesizers Applications

• OTN Muxponders and Transponders
• 10/40/100G network line cards
• GbE/10 GbE/100 GbE Synchronous Ethernet (ITU-T G.8262)
• Carrier Ethernet switches

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation to confirm configuration details. Factory pre-programmed devices utilize unique numerical sequences assigned by ClockBuilder Pro software. Confirm RoHS-6 compliance and Pb-free status as specified in the official datasheet before procurement.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this model for applications requiring ultra-low jitter performance under 100 fs rms. Ensure the design accommodates the 64-QFN 9x9 mm package dimensions. Verify that the required output frequency range does not exceed 720 MHz for differential outputs or 250 MHz for LVCMOS outputs.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This component belongs to the Si5347 family, which utilizes fourth-generation DSPLL technology. It serves as a high-performance jitter-attenuating clock multiplier designed for applications demanding maximum integration and independent timing paths across multiple inputs and outputs.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The Si5347B-Dxxxxx-GMR variant offers a reduced output frequency range up to 350 MHz. The Si5347C/D variants provide similar capabilities but may differ in specific electrical characteristics or feature sets compared to the Si5347A grade.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How does the device handle input clock failure?

The device automatically enters Holdover Mode using stored historical frequency data when the selected input clock becomes invalid, ensuring continuous operation without interruption.

What is the Fastlock feature?

Fastlock allows setting a temporary higher loop bandwidth during lock acquisition to reduce lock time, after which it reverts to the configured lower nominal bandwidth for optimal jitter attenuation.

Can the device switch between gapped clocks?

Yes, the DSPLLs support locking to gapped input clocks with missing periods, producing a periodic non-gapped output clock with an average frequency derived from the input.