SI5368B-C-GQ

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5368B-C-GQ is a jitter-attenuating precision clock multiplier utilizing third-generation DSPLL technology. It accepts four differential or single-ended clock inputs ranging from 2 kHz to 710 MHz and generates five independent outputs spanning 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device operates on a single supply voltage of 1.8 V, 2.5 V, or 3.3 V. It features an integrated loop filter with digitally selectable bandwidths between 60 Hz and 8.4 kHz. Configuration is managed via I2C or SPI interfaces, supporting programmable frequency synthesis without external VCXO components.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any frequency translation combination across the operating range using independent dividers for each input and output clock.
• Provides ultra-low jitter performance meeting OC-192 GR-253-CORE specifications with jitter generation as low as 300 fs rms.
• Supports manual or automatically controlled hitless switching among four clock inputs with phase build-out capabilities.
• Enables SONET frame sync switching and regeneration while supporting ITU G.709 and custom FEC ratios.

Clock Generators, PLLs, Frequency Synthesizers Applications

• SONET/SDH OC-48/STM-16/OC-192/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10/16G Fibre Channel systems
• ITU G.709 and custom FEC line cards
• Wireless basestations
• Data converter clocking

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific ordering suffix against the manufacturer's official documentation to confirm package type, temperature grade, and lead-free compliance status. Ensure the selected variant matches the required operational voltage and interface configuration for the target application design.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when sub 1 ps rms jitter performance is required for high-speed timing applications. Consider the available output signal formats including LVPECL, LVDS, CML, and CMOS. Evaluate power consumption constraints, noting that LVPECL and CMOS formats draw higher current than LVDS or CML at 3.3 V operation.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This device belongs to the Si5368 family of any-frequency precision clock multipliers and jitter attenuators. It is part of Skyworks Solutions' portfolio of timing solutions designed to replace multiple discrete oscillators and clock generators with a single highly flexible integrated circuit.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not provided in the verified source material. Consult the manufacturer's official documentation for cross-reference information or alternative device recommendations.

Clock Generators, PLLs, Frequency Synthesizers FAQ

What is the maximum output frequency supported by the Si5368?

The device generates outputs ranging from 2 kHz to 945 MHz, with select frequencies capable of reaching up to 1.4 GHz.

How is the internal loop filter configured?

The Si5368 features an integrated loop filter with a digitally programmable bandwidth that can be selected between 60 Hz and 8.4 kHz.

Can the device switch between input clocks without interruption?

Yes, the Si5368 supports manual or automatically controlled hitless switching among its four clock inputs, along with phase build-out functionality.