SI5369B-C-GQ

Clock Generators, PLLs, Frequency Synthesizers Overview

The Si5369B-C-GQ is a jitter-attenuating precision clock multiplier utilizing third-generation DSPLL technology. It accepts four clock inputs from 2 kHz to 710 MHz and generates five outputs ranging from 2 kHz to 945 MHz, with select frequencies reaching 1.4 GHz. The device operates on a single 1.8 V, 2.5 V, or 3.3 V supply within an ambient temperature range of -40°C to 85°C. Key electrical parameters include a maximum output frequency of 1.4 GHz (N1=4), a typical jitter generation of 30 ps peak-to-peak (OC-192), and a digital loop bandwidth programmable between 4 Hz and 525 Hz. It features integrated CMOS, LVPECL, CML, and LVDS output formats.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Generates any frequency translation combination across the operating range using independent dividers for each input and output clock.
• Supports hitless switching between input clocks with manual or automatic control, minimizing phase transient propagation.
• Provides digitally programmable PLL loop bandwidth for optimized jitter performance without external components.
• Includes alarm outputs for loss-of-lock, loss-of-signal, and frequency-of-service.

Clock Generators, PLLs, Frequency Synthesizers Applications

• SONET/SDH OC-48/STM-16/OC-192/STM-64 line cards
• GbE/10GbE, 1/2/4/8/10G FC line cards
• ITU G.709 and custom FEC line cards
• Wireless repeaters and wireless backhaul systems

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific suffix 'B-C-GQ' against the manufacturer's ordering guide to confirm package type, speed grade, and tape-and-reel packaging specifications. Ensure the selected variant matches the required output frequency limits and signal format configurations for the target application design.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when sub 1 ps rms jitter performance is required for high-speed timing applications. Consider the available output formats (LVPECL, LVDS, CML, CMOS) and the need for multiple independent input/output frequency translations. Verify that the power dissipation constraints are met if operating at 3.3 V with multiple enabled LVPECL or CMOS outputs.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The Si5369 belongs to Skyworks Solutions' Si536x family of jitter cleaners and clock multipliers. It is designed for high-performance timing applications requiring precise frequency synthesis and jitter attenuation. The device integrates the loop filter and eliminates the need for external VCXO components, offering a compact solution for complex clocking architectures.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Evaluate other members of the Si536x family based on pin compatibility and functional requirements.