SI5380A-D11631-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5380A-D11631-GM is a high-performance, integer-based jitter attenuator and clock multiplier utilizing 4th generation DSPLL technology. It integrates frequency synthesis and jitter attenuation in a digital solution, eliminating the need for external VCXO and loop filter components. The device features four inputs and twelve outputs within a 64-QFN package. It supports differential input frequencies from 11.52 MHz to 737.28 MHz and LVCMOS inputs up to 245.76 MHz. Output frequencies range from 480 kHz to 1.47456 GHz differentially. Key electrical specifications include an ultra-low jitter of 65 fs typ (12 kHz to 20 MHz) and a phase noise floor of –159 dBc/Hz.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Digital frequency synthesis eliminates the requirement for external voltage-controlled oscillators and analog loop filters.
• Supports JESD204B clocking standards including DCLK and SYSREF generation.
• Provides hitless switching capabilities between frequency-locked input clocks.
• Includes programmable jitter attenuation bandwidth ranging from 0.1 Hz to 100 Hz.

Clock Generators, PLLs, Frequency Synthesizers Applications

• JESD204B clock generation
• Remote Radio Units (RRU) and Remote Access Networks (RAN)
• Wireless base stations supporting 3G, GSM, W-CDMA, 4G/LTE, and LTE-A
• Data conversion sampling clocks for ADC, DAC, DDC, and DUC

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify component authenticity through authorized distributors or direct manufacturer channels. Confirm RoHS compliance and Pb-free status prior to integration. Ensure proper handling of moisture-sensitive devices according to standard guidelines. Validate that the specific ordering suffix matches the required packaging configuration for the manufacturing line.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component for applications requiring ultra-low phase noise and high integration levels. Ensure the design accommodates the 64-QFN 9x9 mm package dimensions. Verify that the input signal formats match the supported differential or LVCMOS ranges. Consider the operating temperature range of -40°C to +85°C for environmental compatibility.

Clock Generators, PLLs, Frequency Synthesizers Part Context

This part belongs to the Si5380 family of wireless jitter attenuators and clock multipliers. It is based on Silicon Laboratories' 4th generation DSPLL technology. The device is designed for small cell applications demanding high performance. It serves as a versatile platform for synthesizing multiple integer-related frequencies with superior immunity to board disturbances.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. The datasheet indicates the device is Not Recommended for New Designs. Evaluate alternative models such as the Si5386 if phase adjust capability between DCLK and SYSREF is required.