SI5512B-B15655-GM

Clock Generators, PLLs, Frequency Synthesizers Overview

The Skyworks SI5512B-B15655-GM is a NetSync™ low phase noise jitter attenuating clock generator designed for 5G, eCPRI, SyncE, and IEEE 1588 synchronization. It features 6 inputs and 12 outputs in a 72-lead QFN package (10x10 mm). The device supports integer output frequencies up to 1.2288 GHz and fractional frequencies up to 650 MHz. Typical ultra-low jitter performance is 47 fs RMS. Phase noise specifications include a noise floor of –164 dBc/Hz at 491.52 MHz and –145 dBc/Hz at an 800 kHz offset. It utilizes fifth-generation DSPLL™ and MultiSynth™ technologies.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Supports JESD204B/C Subclass 0 and 1 with DCLK/SYSREF generation
• Independent network synchronization DSPLLs with adjustable DCO
• Instant lock capability for 1PPS and PP2S signals
• Programmable delay at each output with output-to-output skew control

Clock Generators, PLLs, Frequency Synthesizers Applications

• LTE-A and 5G Remote Radio Units (RRU)
• JESD204B/C clock generation
• IEEE 1588 slave clocks (T-TSC) and Telecom Boundary Clocks (T-BC)
• Remote Access Networks (RAN), picocells, and small cells
• Wireless repeaters and mobile fronthaul/backhaul systems

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify the specific B15655 suffix against the official Skyworks datasheet to confirm exact frequency and configuration parameters. Confirm RoHS compliance and Pb-free status prior to procurement. Ensure availability of AccuTime™ IEEE 1588 software if phase synchronization is required. Check for moisture sensitivity level (MSL) requirements during storage and handling.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component for split-board applications where digital and RF functions are separated. It serves as a network synchronizer on the digital board. Verify that the 12-output count meets system requirements, as it lacks some RF-specific features found in the 18-output Si5518 variant. Ensure host processor resources are available for optional AccuTime™ software implementation.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The SI5512 is a 12-output variant within the NetSync family, derived from the 18-output Si5518. It retains full network synchronization functionality but excludes certain RF features like VCXO phase noise reference or OSYNC for JESD204B/C Subclass 2. This makes it suitable for wireless networks splitting digital and RF functions onto separate PCBs.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

The Si5518 offers 18 outputs and additional RF capabilities such as VCXO support. For direct replacement without RF features, verify pinout compatibility and ensure the 12-output limit of the Si5512 suffices for the design.

Clock Generators, PLLs, Frequency Synthesizers FAQ

Does the SI5512 support JESD204B/C Subclass 2?

No, the Si5512 supports JESD204B/C Subclass 0 and 1 only. It does not support Subclass 2 or OSYNC.

What is the maximum integer output frequency?

The maximum integer output frequency is 1.2288 GHz.

Can the device lock to 1PPS and PP2S signals?

Yes, the PPSPLL provides instant lock for 1PPS and PP2S signals with programmable loop bandwidth.