SL16010DCT

Clock Generators, PLLs, Frequency Synthesizers Overview

The SL16010DCT is a low power dissipation spread spectrum clock generator manufactured by Silicon Laboratories. It utilizes a proprietary low jitter PLL to provide two output clocks: a buffered 27.000MHz REFCLK and a synthesized 100.000MHz SSCLK. The device operates on a 3.3V +/-10% power supply with typical current consumption of 13.5mA at CL=15pF. It features internal voltage regulators, supports -10°C to +85°C temperature range, and includes SSEL0/SSEL1 inputs for selecting spread percentages from 0.0% to -3.0%. The component is housed in a 10-pin TDFN package measuring 3x3x0.75 mm.

Clock Generators, PLLs, Frequency Synthesizers Feature Summary

• Proprietary low jitter PLL architecture minimizes cycle-to-cycle and long-term jitter for stable clock generation.
• Configurable spread spectrum modulation reduces system EMI levels through selectable percentage options via digital control pins.
• Integrated crystal oscillator eliminates the need for external oscillators while supporting both crystal and direct clock inputs.

Clock Generators, PLLs, Frequency Synthesizers Applications

• Video Cards
• NB and DT PCs
• HDTV and DVD-R/W
• Routers, Switches and Servers
• Data Communications

Clock Generators, PLLs, Frequency Synthesizers Procurement Notes

Verify that the specific order corresponds to the tape and reel shipping configuration indicated by the DCT suffix. Confirm the operating temperature grade matches the C-grade specification of -10 to +85°C. Ensure the design accounts for the RoHS compliant and Halogen Free status as documented in the ordering information section of the datasheet.

Clock Generators, PLLs, Frequency Synthesizers Selection Notes

Select this component when a fixed 27MHz input and 100MHz output are required with spread spectrum capabilities. Evaluate the load capacitance requirements carefully, as external capacitors must be calculated based on the 4pF pin capacitance and PCB parasitic values. Consider the 3-level logic interface for spread selection if precise EMI optimization is necessary for the target application.

Clock Generators, PLLs, Frequency Synthesizers Part Context

The SL16010DCT is the tape and reel variant of the SL16010DC. Both share identical electrical characteristics, pinouts, and functionality. The distinction lies solely in the packaging method for automated assembly processes. The device belongs to the family of low power clock generators designed for high-speed digital systems requiring strict jitter performance.

Clock Generators, PLLs, Frequency Synthesizers Replacement Considerations

No public confirmed substitute part numbers are available in the provided documentation.

Clock Generators, PLLs, Frequency Synthesizers FAQ

How is the middle logic level achieved for the SSEL0 and SSEL1 pins?

A 5kΩ/5kΩ external resistor divider network connected from VDD to VSS is required to generate the VDD/2 voltage level for the Middle state.

What is the maximum allowable spread percentage for the SSCLK output?

The maximum down spread percentage is -3.0%, selected by setting both SSEL0 and SSEL1 to the High (VDD) logic level.

Can the SL16010DCT operate without an external crystal?

Yes, Pin-1 (XIN/CLKIN) can be driven directly by an external clock signal, in which case Pin-10 (XOUT) should be left unconnected.