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SLB9670VQ20FW785XTMA1 is listed in the Application Specific Microcontrollers range at ChipApex. The manufacturer field lists Infineon Technologies. Its product description is IC TPM VQFN. Review the specifications below when checking this part for your BOM.
The SLB9670VQ20FW785XTMA1 is an Infineon OPTIGA™ TPM 2.0 security controller in a PG-VQFN-32-13 package. It complies with TCG Family 2.0 specifications and holds FIPS 140-2 Level 2 certification (Certificate Number 3492). The device features an SPI interface supporting up to 43 MHz at 3.3V or 22.5 MHz at 1.8V. It provides 24 PCRs, minimum 6962 bytes of free NV memory, and supports ECC NIST P-256 and RSA 2048 cryptography. Operating voltage ranges from 1.65 V to 1.95 V or 3 V to 3.6 V, with a standard temperature range of -20 °C to +85 °C.
Verify the ordering suffix XTMA1 corresponds to the PG-VQFN-32-13 package and standard temperature range (-20..+85°C). Confirm firmware version FW7.85 matches system requirements. Ensure supply voltage rails align with the specified 1.65–1.95 V or 3–3.6 V operational ranges.
Select this part for standard temperature applications (-20..+85°C); use the XQ variant for enhanced ranges (-40..+85°C). Ensure host SPI signals are compatible with Schmitt-Trigger inputs. Verify that the host platform meets Intel TXT, Microsoft Windows, or Google Chromebook certification criteria if required for deployment.
This component belongs to the OPTIGA™ TPM SLB 9670 family, which includes the SLB 9670VQ2.0 (standard temp) and SLB 9670XQ2.0 (enhanced temp). It is pin-compatible with the previous OPTIGA™ TPM SLB 9670 TPM 1.2 version, facilitating upgrades.
Publicly confirmed substitute part numbers are not provided in the source material. For direct pin-compatible replacement within the same family, consider the SLB9670VQ20FW786XTMA1 or other variants listed in the Bill of Material for evaluation boards.
The maximum SCLK frequency is 43 MHz when VDD is typically 3.3V with a slew rate ≥ 1V/ns, or 22.5 MHz when VDD is typically 1.8V with a slew rate ≥ 1V/ns.
Power management is handled internally without explicit standby modes. The device automatically enters a low-power state after each successful command/response transaction and wakes immediately upon a new SPI bus transaction.
The device supports symmetric cryptography including SHA-256, SHA-1, and HMAC. Asymmetric cryptography includes ECC NIST P-256, ECC256, ECDH, RSA1024, and RSA2048.
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