SN65LVDS117DGG

Overview

The SN65LVDS117DGG is a dual 8-port LVDS repeater manufactured by Texas Instruments. It integrates two identical banks, each containing one differential line receiver and eight differential line drivers. The device operates on a single 3 V to 3.6 V supply with a typical current of 122 mA. It supports data signaling rates up to 400 Mbps and clock frequencies up to 400 MHz. Key electrical parameters include a propagation delay of less than 4.5 ns, output skew under 550 ps, bank skew under 150 ps, and part-to-part skew under 1.5 ns. The component is housed in a 64-pin Thin Shrink Small-Outline Package (TSSOP) and functions within an operating temperature range of -40 °C to +85 °C.

Feature Summary

• Integrates two independent banks, each comprising one LVDS receiver and eight LVDS drivers for simultaneous signal distribution.
• Provides individual enable logic for each output pair alongside a global bank enable control to manage signal paths.
• Features built-in fail-safe circuitry that forces the receiver output high when input lines are open-circuited.
• Delivers precise timing alignment through low pulse skew characteristics inherent to the balanced signaling architecture.

Applications

• System clock and data distribution trees requiring precise timing alignment.
• Point-to-point or point-to-multipoint baseband data transmission over controlled impedance media.
• Signal buffering and splitting for printed-circuit board traces, backplanes, or cables.

Procurement Notes

Verify the specific ordering suffix against the manufacturer's latest documentation to confirm package type and reel specifications. Ensure compliance with RoHS directives and check moisture sensitivity levels prior to surface-mount assembly. Confirm availability status as production data may be subject to change without notice.

Selection Notes

Select this component when a design requires distributing two differential signals to multiple destinations with minimal skew. Compare against the SN65LVDS109 if only four outputs per bank are sufficient. Verify that the system load matches the 100 Ω differential termination requirements specified in the datasheet.

Part Context

This device belongs to the SN65LVDS1xx family of LVDS splitters and repeaters. It shares architectural similarities with the SN65LVDS109 but offers double the output density per bank. Both devices utilize the same low-voltage differential signaling protocol defined by ANSI EIA/TIA-644.

Replacement Considerations

The SN65LVDS109 serves as a lower-density alternative within the same family. Cross-referencing should focus on pin compatibility and functional equivalence regarding LVDS signaling standards.