SN74ALS373ADBR

Overview

The SN74ALS373ADBR is an octal transparent D-type latch with 3-state outputs manufactured by Texas Instruments. It operates within a supply voltage range of 4.5 V to 5.5 V and supports a commercial temperature range of 0°C to 70°C. The device features buffered control inputs and PNP inputs that reduce DC loading on data lines. Key electrical characteristics include a low-level output current of 24 mA and a high-level output current of -2.6 mA at 5V. Propagation delays from D to Q range from 2 ns to 19 ns, while the LE-to-Q delay ranges from 1 ns to 27 ns under specified load conditions.

Feature Summary

• Octal transparent D-type latches designed for driving highly capacitive or relatively low-impedance loads
• Buffered control inputs and PNP inputs to reduce DC loading on data lines
• Three-state bus-driving true outputs capable of driving bus lines without interface components

Applications

• Implementing buffer registers
• I/O ports
• Bidirectional bus drivers
• Working registers

Procurement Notes

Verify the SSOP package designation (DB) and tape-and-reel carrier type when sourcing. Confirm RoHS compliance and lead finish specifications against the latest Package Option Addendum. Ensure the operating temperature range matches the application requirements. Cross-reference the manufacturer part number with distributor catalogs to confirm active production status and availability.

Selection Notes

Select this component for applications requiring parallel access loading and high-drive capability. The ALS series offers faster switching speeds compared to standard LS logic. Consider the 3-state output feature for bus-oriented systems where multiple devices share common lines. Verify input voltage levels align with the driving source logic family.

Part Context

This part belongs to the SN74ALS373A family of octal transparent D-type latches. It shares functional similarities with the SN74AS373 but differs in drive strength and speed characteristics. The device is available in various packages including SOIC, PDIP, and SSOP, catering to different PCB layout and density requirements.

Replacement Considerations

SN74ALS373ADWR

FAQ

How does the Output Enable (OE) input affect internal latch operations?

The OE input places the outputs in a high-impedance state but does not affect the internal operations of the latches. Data can be retained or entered while the outputs are disabled.

What is the function of the Latch Enable (LE) input?

When LE is high, the Q outputs follow the D inputs. When LE goes low, the outputs are latched at the logic levels present at the D inputs at that moment.