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SN74AUP1G98YFPR is listed in the Gates And Inverters - Multi-Function, Configurable range at ChipApex. The manufacturer field lists Texas Instruments. Its product description is IC GATE MULT-FUNC CONFIG 6DSBGA. Review the specifications below when checking this part for your BOM.
The SN74AUP1G98YFPR is a single configurable logic gate from Texas Instruments' AUP family, housed in a 6-DSBGA package. It operates within a supply voltage range of 0.8 V to 3.6 V, supporting mixed-mode signal operation with 3.6-V I/O tolerance. The device features Schmitt-trigger inputs for improved noise immunity and supports partial-power-down applications via the Ioff circuitry. Key electrical parameters include a maximum propagation delay of 5.3 ns at 3.3 V, a typical low input capacitance of 1.5 pF, and a maximum static current of 0.9 µA.
Verify the specific suffix YFPR corresponds to the 6-DSBGA package and reel packaging configuration. Confirm RoHS compliance status and ensure the component matches the SN74AUP1G98 functional specification. Check for any recent product change notices or lifecycle status updates from Texas Instruments before finalizing procurement.
Select this component when a single gate requires multiple logic function configurations without additional external components. The AUP family is suitable for designs needing wide voltage operation and low static power. Ensure the application benefits from Schmitt-trigger input characteristics and partial-power-down support compared to standard logic gates.
This part belongs to the SN74AUP1Gxx series of single configurable logic gates. It utilizes Texas Instruments' NanoStar package technology, which uses the die as the package to minimize size. The AUP family is designed to meet industry low-power needs while maintaining excellent signal integrity across the entire supply voltage range.
Direct replacements must match the 6-DSBGA package and AUP logic family specifications. Verify that substitute parts support the same configurable logic functionality and Schmitt-trigger input requirements. Ensure compatibility with partial-power-down modes if required by the design.
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