SN74LVC373AGQNR

Latches Overview

The SN74LVC373AGQNR is an octal transparent D-type latch with 3-state outputs from the Texas Instruments LVC series. It operates within a supply voltage range of 1.65 V to 3.6 V and features inputs that accept voltages up to 5.5 V, supporting mixed-mode signal operation. The device provides high drive capability with output currents reaching 24 mA at 3.3 V. Propagation delay is specified at a maximum of 6.8 ns at 3.3 V. It includes Ioff circuitry for partial-power-down support and exhibits latch-up performance exceeding 250 mA per JESD 17 standards.

Latches Feature Summary

• Operates from 1.65 V to 3.6 V with inputs accepting voltages up to 5.5 V
• Ioff feature supports live-insertion, partial-power-down mode, and back-drive protection
• Latch-up performance exceeds 250 mA per JESD 17 standards
• ESD protection exceeds 2000-V human-body model and 1000-V charged-device model

Latches Applications

• Network switches
• TV set-top boxes
• Motor drives
• PCs and notebooks

Latches Procurement Notes

Verify the specific package configuration associated with the GQN suffix against the manufacturer's official orderable addendum. Confirm the operating temperature range and RoHS compliance status directly with the supplier documentation prior to integration. Ensure the component meets all absolute maximum ratings for your target application environment.

Latches Selection Notes

Select this component for designs requiring octal data latching with tri-state bus interfacing in low-voltage environments. The 5.5 V tolerant inputs facilitate direct connection to legacy 5 V logic without level shifting. The high drive current capability makes it suitable for driving multiple loads or long traces on PCBs.

Latches Part Context

This part belongs to the SNx4LVC373A family of octal transparent D-type latches. The family offers various package options including SSOP, SOIC, TSSOP, and VQFN. The LVC series is designed for 1.65-V to 3.6-V VCC operation, providing compatibility with modern low-power digital systems while maintaining robust noise immunity.

Latches Replacement Considerations

SN74LVC373ADBR

Latches FAQ

How does the Ioff feature function?

The Ioff circuitry disables the outputs when VCC is 0 V, preventing damaging current backflow through the device during partial-power-down or power-off states.

What is the behavior of the outputs when OE is high?

When the output-enable (OE) input is high, the outputs enter a high-impedance state, neither loading nor driving the bus lines significantly.