STG4260BJR

Overview

The STG4260BJR is a low voltage dual SPDT analog switch fabricated in silicon gate C2MOS technology. It operates from 1.65 V to 4.8 V with separate supply voltages for the switch and control pins. The device features an ON resistance of 0.40 Ω typ at VCC = 4.3 V, quiescent current of 0.2 µA max at 85 °C, and propagation delay of 0.12 ns typ at 3.0 V. It includes break-before-make functionality, 15 kV IEC-61000-4-2 ESD protection on common pins, and latch-up performance exceeding 100 mA per JESD 78 Class II. The component is housed in a Flip-chip 12 package (1.9 x 1.4 mm) and supports -40 °C to 85 °C operating temperature.

Feature Summary

• Dual single-pole double-throw (SPDT) switching architecture with independent channel control via SEL inputs
• Break-before-make switching mechanism to prevent signal overlap during transitions
• High electrostatic discharge immunity with 15 kV contact discharge protection on common ports
• Ultra-low power consumption suitable for battery-operated portable applications

Applications

• Mobile phones
• Portable consumer electronics
• Signal routing in communication systems

Procurement Notes

Verify the specific ordering code STG4260BJR against official manufacturer documentation to confirm the Flip-chip 12 packaging and tape-and-reel configuration. Ensure that the logic supply voltage requirements align with system design constraints before procurement. Confirm environmental compliance status through ECOPACK specifications provided by the manufacturer.

Selection Notes

Select this component when designing circuits requiring low voltage operation between 1.65 V and 4.8 V with minimal signal distortion. Consider the 0.40 Ω typical ON resistance and high isolation characteristics for precision analog signal routing. Evaluate the separate control supply pin capability if level shifting or distinct logic voltage domains are required in the application design.

Part Context

The STG4260 belongs to STMicroelectronics' family of low voltage analog switches designed for portable devices. It utilizes C2MOS technology to achieve high speed and low power dissipation. The device provides two independent SPDT switches controlled by dedicated selection inputs, offering flexibility in multiplexer and demultiplexer configurations within compact footprints.

Replacement Considerations

Consult official replacement lists for direct equivalents. Verify pin compatibility and electrical parameters such as ON resistance and voltage ranges before substituting with other dual SPDT switches.

FAQ

What is the maximum ESD protection rating for the common pins?

The common pins (D1 and D2) offer 15 kV IEC-61000-4-2 contact discharge ESD protection.

How does the break-before-make feature function?

The device ensures that one switch opens completely before the other closes, preventing signal overlap during state transitions.

What is the typical propagation delay at 3.0 V?

The typical propagation delay is 0.12 ns when the supply voltage is 3.0 V.