SY89840UMG

Overview

The SY89840UMG is a Precision LVPECL Runt Pulse Eliminator (RPE) 2:1 multiplexer designed for redundant source switchover applications. It operates from a 2.5V ±5% or 3.3V ±10% supply voltage and supports frequencies up to 1.5 GHz. The device features an in-to-out propagation delay of less than 880 ps and output rise/fall times under 190 ps. It provides ultra-low jitter with typical RMS phase jitter of 140 fs and MUX crosstalk-induced jitter of 0.7 ps rms. The component accepts AC or DC-coupled differential inputs as small as 100 mV and delivers an 800 mV LVPECL output swing.

Feature Summary

• Eliminates runt pulses during clock switchover to ensure glitch-free operation
• Includes fail-safe input protection to prevent metastable conditions when selected clocks fail
• Features unique 3-pin input termination architecture supporting CML, PECL, and LVDS signals without external level shifting

Applications

• Redundant clock switchover systems
• Failsafe clock protection circuits
• Enterprise server infrastructure
• Test and measurement equipment

Procurement Notes

Verify the specific ordering suffix to confirm package type and reel configuration. Confirm that the supplier documentation references the Micrel datasheet accurately. Ensure the component meets RoHS compliance standards required for your assembly process. Check for any recent product change notifications regarding manufacturing sites or materials.

Selection Notes

Select this component when glitch-free switchover between two asynchronous clock sources is critical. It is suitable for designs requiring low jitter performance and flexible input interface compatibility. Consider the QFN-16 package constraints and thermal requirements for high-density layouts.

Part Context

This part belongs to the Precision Edge family of high-speed logic devices originally developed by Micrel, which was acquired by Microchip Technology. The series focuses on precision timing solutions with advanced signal integrity features for demanding digital communication environments.

Replacement Considerations

SY89841UMG

FAQ

How does the Fail-Safe Input function protect against clock failure?

If the selected input pair drops below the minimum amplitude requirement (less than 100mV single-ended or 200mV differential), the output latches to the last valid clock state to prevent oscillations.

What is the purpose of the CAP pin?

The CAP pin connects to an external capacitor to control the Power-On Reset delay, ensuring the internal RPE logic starts in a known state. Tying it directly to VCC disables the RPE function.