SY89873LMI-TR

Overview

The SY89873LMI-TR is a 3.3V low-skew, low-jitter clock divider and fanout buffer featuring precision LVDS outputs. It accepts any high-speed differential input (CML, LVPECL, HSTL, or LVDS) via an internal termination network accessible through the VT pin. The device provides two output banks: Bank A passes the undivided input clock, while Bank B offers programmable division ratios of ÷2, ÷4, ø8, or ÷16. Key AC specifications include a maximum output toggle frequency exceeding 2.0GHz, an input frequency capability over 3.0GHz, propagation delay under 800ps, and within-device skew below 15ps.

Feature Summary

• Accepts CML, LVPECL, HSTL, or LVDS inputs with unique VT pin for DC/AC coupling flexibility
• Two matched-delay LVDS output banks: Bank A (pass-through) and Bank B (÷2, ÷4, ÷8, ÷16)
• Low jitter performance with less than 1ps RMS cycle-to-cycle jitter
• High-speed operation with >2.0GHz fMAX output and <15ps within-device skew

Applications

• SONET/SDH line cards
• Transponders
• High-end multiprocessor servers

Procurement Notes

Verify that the 'MI' suffix corresponds to the QFN-16 package variant as documented in the official datasheet. Confirm the specific ordering code matches the tape and reel configuration required for automated assembly processes.

Selection Notes

Select this component when a single supply voltage is needed to interface between different differential logic standards and generate multiple divided clock frequencies. Ensure the application requires LVDS outputs rather than LVPECL, which would necessitate the SY89871U model.

Part Context

This part belongs to Micrel’s Precision Edge timing and distribution family. For 2.5V applications, the SY89872U is the equivalent voltage variant. Devices requiring LVPECL outputs instead of LVDS should consider the SY89871U.

Replacement Considerations

Public confirmed substitute part numbers only; omit otherwise.