TDA9855/V2,112

Overview

The TDA9855 is a bipolar-integrated BTSC stereo/SAP decoder and audio processor designed for TV applications. It features an I2C-bus controlled quasi alignment-free BTSC stereo decoder with automatic channel separation adjustment and integrated filters. The device includes a dbx noise reduction circuit, SAP demodulator, and a comprehensive audio processor with volume, bass, treble, and loudness controls. Operating on an 8V to 9V supply, it delivers a typical supply current of 75 mA. Key performance metrics include a stereo channel separation of 35 dB at 300 Hz/3 kHz and a total harmonic distortion of 0.2%.

Applications

• TV sets requiring BTSC stereo decoding
• Consumer audio signal processing systems
• Television receivers with SAP functionality

Procurement Notes

Verify the specific package variant required, as the TDA9855 is available in SDIP52 and PLCC68 packages. Confirm that the design supports the necessary licensing requirements associated with this product. Ensure the application circuit includes the specified external components, such as the ceramic resonator and electrolytic capacitors, for proper operation.

Selection Notes

Select the TDA9855 for designs requiring integrated BTSC decoding and audio processing in a single IC. The SDIP52 package is suitable for through-hole mounting, while the PLCC68 offers a surface-mount option. Consider the 8V-9V supply requirement and the need for non-volatile memory to store alignment data after power cycles.

Part Context

The TDA9855 is part of NXP's (formerly Philips Semiconductors) line of analog mixed-signal integrated circuits. It serves as a specialized component for television audio systems, combining RF demodulation support with baseband audio processing. The device is documented in a product specification dated November 1997, superseding earlier July 1994 data.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. The TDA9855WP is a pin-compatible alternative package variant (PLCC68) of the same functional device.

FAQ

How is the stereo channel separation adjusted?

The stereo channel separation can be adjusted automatically via an I2C-bus procedure or manually by varying spectral and wideband data settings.

What is the maximum input voltage level for the composite signal?

The maximum input signal voltage level (RMS value) at the COMP pin is 2 V.

Does the device support zero-crossing mute?

Yes, all channels include independent zero-crossing detectors, allowing mute execution to be synchronized with the signal zero-crossing to avoid audible pops.