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The TE0820-02-02EG-1EA is a System-on-Module integrating an AMD Zynq UltraScale+ ZU3EG MPSoC in a 784-pin package. It features dual-core Cortex-A53 and dual Cortex-R5 processors, alongside programmable logic with 132 HP I/Os. The module includes 1 GByte of 32-bit DDR4 SDRAM, 4 GByte eMMC, and dual SPI flash. Interfaces include Gigabit Ethernet via Marvell Alaska 88E1512, USB 2.0 ULPI, four GTR transceivers, and DisplayPort. Operating temperature ranges from -40°C to +105°C.
Verify the specific ordering suffix against the manufacturer's current production list to confirm availability and revision status. Ensure carrier board designs comply with the mechanical mating height and electrical specifications defined in the Technical Reference Manual. Confirm that the required memory configuration matches the delivered unit, as variants may differ in RAM and storage capacity.
Select this module when a compact 4x5 cm form factor is required with integrated MPSoC capabilities. The ZU3EG variant offers a balance of processing performance and I/O density. Consider the available GTR lanes for high-speed serial applications and verify that the on-board peripherals like Ethernet and USB meet the system interface requirements without additional external components.
This component belongs to the Trenz Electronic TE0820 family of System-on-Modules designed for the 4x5 cm standard footprint. These modules are engineered for high reliability in industrial environments and are mechanically compatible with other modules in the same series. They provide a complete computing solution with integrated power management and memory, simplifying carrier board design.
Check for updated revisions within the TE0820 series that may offer different processor options or memory configurations. Verify compatibility with existing carrier boards if substituting with other TE0820 variants. Consult the manufacturer for end-of-life notifications or recommended alternative modules if the specific ZU3EG configuration is discontinued.
The module can boot from either QSPI Flash or SD Card, determined by the state of the MODE pin on the B2B connector JM1. Low selects SD Card boot, while High selects Flash boot.
JTAG access is controlled by the JTAGEN pin on connector JM1. Pulling it low routes JTAG to the Zynq MPSoC, while pulling it high routes it to the System Controller CPLD.
The High Performance (HP) I/O banks (64, 65, and 66) support a maximum voltage of 1.8V.