TE0820-02-03CG-1EA

Overview

The TE0820-02-03CG-1EA is a System-on-Module integrating the Xilinx Zynq UltraScale+ ZU3EG MPSoC. It features a dual-core Cortex-A53 application processing unit and dual Cortex-R5 real-time processing units. The module includes 1 GByte of 32-bit DDR4 SDRAM, 4 GByte eMMC storage, and dual 256 Mbit Quad SPI flash memory. Connectivity is provided by a Marvell Alaska 88E1512 Gigabit Ethernet PHY and a Microchip USB3320 ULPI transceiver. The system controller utilizes a Lattice MachXO2 CPLD.

Feature Summary

• Integrates Xilinx Zynq UltraScale+ ZU3EG with dual Cortex-A53 and dual Cortex-R5 cores
• Includes on-board Marvell Gigabit Ethernet PHY and Microchip USB 2.0 ULPI PHY
• Features Lattice MachXO2 System Controller CPLD for power management and boot control
• Provides four high-speed serial I/O interfaces including PCIe, SATA, DisplayPort, and USB 3.0

Applications

• Industrial automation controllers requiring embedded processing
• Medical imaging systems utilizing high-speed data acquisition
• Aerospace and defense avionics platforms
• High-performance measurement and test equipment

Procurement Notes

Verify component availability as this specific variant may be discontinued or subject to supply constraints. Confirm the exact ordering suffix corresponds to the required processor speed grade and memory configuration. Request current lifecycle status documentation from Trenz Electronic to ensure long-term project viability. Validate that carrier board designs support the specified B2B connector mechanical ratings and voltage levels.

Selection Notes

Select this module when a compact 4x5 cm form factor is required alongside Zynq UltraScale+ processing capabilities. Ensure the carrier board design accommodates the 1.8V I/O voltage requirements for the high-performance banks. Verify that the available MGT lanes and PS MIOs meet the specific interface bandwidth needs. Consider the thermal dissipation requirements associated with the integrated switch-mode power supplies and MPSoC.

Part Context

This module belongs to the TE0820 series, which provides standard 4 x 5 cm footprint modules based on Xilinx Zynq UltraScale+ MPSoCs. The series is designed for mechanical compatibility across variants, allowing designers to upgrade processing power without changing the carrier board layout. Trenz Electronic manufactures these modules to support rapid prototyping and production in industrial and embedded markets.

Replacement Considerations

Consult Trenz Electronic for current active replacements within the TE0820 family. Verify if newer silicon revisions offer equivalent pinouts and functionality. Check for updated technical manuals regarding any changes in power sequencing or peripheral configurations compared to the legacy TRM v.51 documentation.

FAQ

How is JTAG access managed between the MPSoC and the CPLD?

JTAG access is controlled via Pin 89 (JTAGEN) on the B2B connector JM1. When pulled low, the interface routes to the Xilinx Zynq MPSoC; when pulled high, it routes to the System Controller CPLD.

What are the default boot options for this module?

The module supports booting from either QSPI Flash or an SD Card. The selection is determined by the state of the MODE pin on the B2B connector JM1 during power-up.

Which components provide the reference clocks for the GTR transceivers?

Three clock sources are available: B505_CLK0 can be supplied by the carrier board via the B2B connector, while B505_CLK1 and B505_CLK3 are generated by the on-board Si5338A programmable clock generator.