TE0820-04-2BI21FL

Overview

The Trenz Electronic TE0820-04-2BI21FL is a System-on-Module integrating a Xilinx Zynq UltraScale+ MPSoC within a 40 x 50 mm industrial form factor. It features dual 8 Gb DDR4 SDRAM chips operating at 2400 Mbps, two 512 Mb QSPI flash memories for configuration, and an 8 GByte eMMC memory device. The module includes a Lattice MachXO2 CPLD for system control, a Marvell Alaska 88E1512 Gigabit Ethernet PHY, and a Microchip USB2.0 ULPI transceiver. It provides four GTR transceivers and supports DisplayPort output up to 4k resolution.

Feature Summary

• Integrates Xilinx Zynq UltraScale+ MPSoC with Mali-400 MP2 GPU
• Includes on-board Lattice MachXO2 CPLD for system management
• Provides high-speed connectivity via PCIe, SATA 3.1, and DisplayPort
• Features rugged construction suitable for shock and high vibration environments

Applications

• Industrial automation and machine control systems
• High-performance embedded data acquisition
• Medical imaging and diagnostic equipment
• Automotive infotainment and cockpit displays
• Network infrastructure and communication gateways

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current product matrix to ensure component availability and revision alignment. Confirm that the selected variant matches the required processor speed grade and temperature rating for the target deployment environment. Review the latest technical reference manual for any recent hardware revisions or pinout modifications before finalizing procurement specifications.

Selection Notes

Select this module when a compact 4x5 cm footprint is required alongside significant processing power from the Zynq UltraScale+ architecture. Ensure the carrier board design accommodates the Samtec Razor Beam connectors and supports the necessary power distribution for the integrated regulators. Evaluate thermal requirements carefully, as performance depends on the cooling solution and ambient conditions within the enclosure.

Part Context

This module belongs to the TE0820 series of System-on-Modules designed by Trenz Electronic. The series utilizes the 4x5 cm form factor to provide mechanical compatibility across different processor variants. These modules are engineered for industrial applications requiring robust performance in harsh environments, offering a balance of computational density and interface versatility.

Replacement Considerations

Consult the official discontinuation notification if sourcing legacy inventory. Verify electrical compatibility with existing carrier boards, particularly regarding connector mating heights and voltage levels. Check for updated firmware versions for the on-board CPLD and clock generators to ensure proper initialization sequences are maintained during replacement.

FAQ

How is JTAG access managed between the FPGA and the CPLD?

JTAG access is controlled via pin 89 (JTAGEN) on connector JM1. Pulling this pin low routes the JTAG interface to the Xilinx Zynq MPSoC, while pulling it high routes it to the Lattice MachXO2 CPLD.

What is the default boot mode configuration for the module?

The default boot mode is determined by the MODE pin state. A high level selects QSPI boot, while a low level selects SD Card boot. This can be modified using alternative CPLD firmware.

Which components are pre-programmed upon delivery?

Upon initial delivery, only the Lattice MachXO2 CPLD is programmed with the TE0820 CPLD1 firmware. The QSPI flash, eMMC, DDR4, and programmable clock generator are not programmed.