TE0820-04-50121MA

Overview

The TE0820-04-50121MA is a 4 x 5 cm industrial module integrating a Xilinx Zynq UltraScale+ MPSoC with dual 8 Gb DDR4 SDRAM operating at 2400 Mbps, 64 Gb eMMC storage, and two 512 Mb QSPI flash chips. It features a Lattice MachXO2 CPLD for system management, Marvell Alaska 88E1512 Gigabit Ethernet PHY, and Microchip USB2.0 ULPI transceiver. The module provides four MGT lanes via B2B connectors and supports PCIe, SATA, and DisplayPort interfaces.

Feature Summary

• Integrated Lattice MachXO2 CPLD manages power sequencing, reset generation, and JTAG routing between the FPGA and carrier board.
• Dual 8 Gb DDR4 SDRAM chips provide high-bandwidth volatile memory for complex processing tasks.
• On-board peripherals include Gigabit Ethernet and USB 2.0 OTG support without external components.
• Four MGT lanes are directly accessible via high-speed connectors for serial communication protocols.

Applications

• Industrial automation controllers requiring robust processing and connectivity
• Medical imaging systems needing high-speed data acquisition and display output
• Aerospace and defense avionics utilizing ruggedized embedded computing platforms
• Test and measurement equipment requiring precise timing and signal processing

Procurement Notes

Verify the specific Zynq UltraScale+ MPSoC variant (ZU2 to ZU5) and speed grade required for your application, as these determine performance characteristics. Confirm that the initial delivery state includes pre-programmed CPLD firmware while other memories remain unprogrammed. Ensure compatibility with your carrier board's mechanical footprint and electrical interface requirements before finalizing procurement.

Selection Notes

Select this module when a compact form factor is needed alongside significant I/O capabilities including PCIe and SATA. Consider the temperature range requirements, as components cover at least the industrial range but usage depends on cooling design. Evaluate the need for specific boot modes, as the CPLD firmware determines whether QSPI or SD Card booting is utilized by default.

Part Context

This module belongs to the Trenz Electronic TE0820 family of System-on-Modules based on Xilinx Zynq UltraScale+ MPSoCs. These modules are designed for mechanical and electrical compatibility within their form factor class, allowing for easy integration into various carrier boards. The TE0820 series targets applications demanding high performance in a small footprint, leveraging the versatility of the Zynq architecture.

Replacement Considerations

Direct replacements must match the 4 x 5 cm form factor and pinout compatibility. Verify if alternative modules from the same family offer different SoC variants or memory configurations that better suit specific performance needs. Ensure any substitute maintains the same peripheral integration, such as the CPLD functionality and Ethernet/USB PHYs, to minimize carrier board redesign efforts.

FAQ

How is JTAG access controlled between the FPGA and the CPLD?

JTAG access is controlled by pin 89 (JTAGEN) on connector JM1. Pulling this pin low routes JTAG to the Xilinx Zynq MPSoC, while pulling it high routes it to the Lattice MachXO2 CPLD.

What is the default boot mode configuration?

The default boot mode is determined by the MODE pin state. A high level selects QSPI boot, while a low level selects SD Card boot. This can be modified using specific CPLD firmware versions.

Which on-board devices are connected to the I2C bus?

The on-board I2C bus connects to the programmable clock generator (Si5338A) at addresses 0x70/0x71 and the EEPROM at address 0x50. These are connected to MIO38 (SCL) and MIO39 (SDA).