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TLV320AIC12KIRHBT is listed in the Codecs range at ChipApex. The manufacturer field lists Texas Instruments. Its product description is IC VOICE CODEC 16BIT SER 32VQFN. Review the specifications below when checking this part for your BOM.
The TLV320AIC12KIRHBT is a low-power, highly integrated mono voice codec featuring a 16-bit oversampling sigma-delta ADC and DAC. It operates with a digital core voltage of 1.65 V to 1.95 V, digital I/O from 1.1 V to 3.6 V, and analog supplies of 2.7 V to 3.6 V. The device supports sampling rates up to 26 ksps with on-chip filters or 104 ksps when bypassed. Key performance metrics include an SNR of 84 dB for the ADC and 92 dB for the DAC. Power consumption is 17.8 mW at 3.3 V in standard operation. It utilizes SMARTDM and I2C/S2C interfaces.
Verify the specific ordering suffix IRHBT confirms the QFN-32 package and industrial temperature range (-40°C to 85°C). Ensure the design accommodates the thermal pad connection to DRVDD as specified in the datasheet. Confirm that the host system supports the required SMARTDM or I2C/S2C interface protocols for proper initialization and data transfer.
Select this component for applications requiring a single-channel mono codec with integrated audio output drivers. The 'K' designation indicates industrial temperature rating and enhanced features compared to non-K variants. Verify that the available supply voltages match the separate requirements for the digital core, digital I/O, and analog sections to ensure correct biasing and operation.
This part belongs to the TLV320AIC1x family of low-power audio codecs. The AIC12K variant specifically includes the 16-ohm speaker driver, distinguishing it from the AIC13, AIC14, and AIC15 models which lack this output stage. The RHB suffix denotes the QFN-32 package type, offering a compact footprint suitable for space-constrained portable designs.
TLV320AIC12KIDBTR (TSSOP-30 package)
The OUTP2 and OUTP3 outputs can drive a minimum load resistance of 16 ohms.
The device supports a maximum master clock frequency of 100 MHz to derive internal clocks for the sigma-delta analog interface.
Yes, the device allows different sampling rates for each device in a cascade, but within a single unit, the ADC and DAC typically share the same conversion rate determined by the frame sync.
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