TS68020MF1-20

Overview

The TS68020MF1-20 is a high-performance 32-bit microprocessor from the TS68000 family, implemented in HCMOS technology. It features a 32-bit data bus and address bus with an on-chip instruction cache to improve performance. The device operates at a maximum clock frequency of 20 MHz and requires a 5.0 VDC power supply (±10%). It utilizes a 132-pin Ceramic Quad Flat Pack (CQFP) package and supports an operating temperature range of -55°C to +125°C.

Feature Summary

• Object code compatible with earlier TS68000 microprocessors while providing addressing mode extensions for high-level language support.
• Features a fast on-chip instruction cache that accelerates instructions and improves bus bandwidth.
• Includes a co-processor interface designed for companion 32-bit peripherals such as floating-point units.
• Supports full virtual memory and virtual machine capabilities with dynamic bus sizing for various memory configurations.

Applications

• Video graphics applications utilizing new bit field data types.
• Systems requiring co-processor interfaces for floating-point operations.
• Virtual memory and virtual machine environments.

Procurement Notes

Verify the specific suffix 'F' indicates the CQFP 132 ceramic package configuration. Confirm the '-20' designation corresponds to the 20 MHz speed grade. Ensure compliance with MIL-STD-883 Class B or DESC 5962 standards if required by the application specifications.

Selection Notes

Select this component when a 32-bit architecture with backward compatibility to the 16-bit TS68000 is required. Consider the integrated instruction cache for performance needs. Verify thermal management requirements for the CQFP package within the specified military temperature range.

Part Context

This part belongs to the TS68000 family of microprocessors. It represents the first full 32-bit implementation of the series, evolving from previous 16-bit designs. The device maintains software compatibility with the family while introducing 32-bit internal structures and expanded instruction sets.

Replacement Considerations

TS68020MF1B/C16

FAQ

What is the function of the Cache Disable (CDIS) signal?

The CDIS signal dynamically disables the on-chip instruction cache to assist emulator support during development and debugging.

How does the TS68020 handle bus arbitration?

The processor uses Bus Request (BR), Bus Grant (BG), and Bus Grant Acknowledge (BGACK) signals to manage bus mastership transitions between external devices and the processor.