SEARCH
— IC芯片 | 连接器 | 传感器 | 被动器件 —
The TSDP1808X1NEGXZAX is an ultra low-power, high-performance octal PDM to linear PCM converter from Tempo Semiconductor. It supports Digital MEMS Microphone (DMIC) inputs with sample rates up to 6.144MHz and output sampling rates ranging from 8kHz to 384kHz. The device features a dynamic range exceeding 142dB SNR/DNR/THD+N in the 20Hz to 20kHz band. It operates on a single 1.71V to 3.465V supply, drawing 2.68mA in 8-channel TDM mode at 48kHz. The component is housed in a 3x3mm, 20-lead QFN package.
Verify the specific ordering suffix against the manufacturer's datasheet to confirm temperature grade and packaging type. The 'I' suffix indicates Industrial temperature range (-40°C to 85°C), while absence denotes Commercial range (0°C to 70°C). The 'ZAX8' suffix specifies Tape & Reel packaging, whereas 'ZAX' indicates Tray packaging. Confirm these details match the design requirements before procurement.
Select this component for designs requiring direct conversion of multiple PDM microphones to linear PCM without external DSP processing. Ensure the host system provides valid SCLK and LRCLK signals within the specified frequency ranges. Verify that the required oversampling mode and word length configurations align with the available OS_MODE pin settings and supported SCLK to LRCLK ratios.
This part belongs to the TSDP18xx series of audio sample rate converters. It serves as a bridge between digital MEMS microphones and audio processors or codecs. The series includes variants with different temperature ratings and packaging options, such as TSDP1808X1NEGIZAX8 for industrial use in tape and reel format.
Direct substitutes are not explicitly listed in the provided documentation. Designers should evaluate other Tempo Semiconductor audio interface ICs or similar octal PDM-to-PCM converters based on pin compatibility, package dimensions, and electrical specifications.
The device supports output sampling rates ranging from 8kHz up to 384kHz.
The device automatically powers down to consume less than 1uA when the SCLK signal is stopped or removed.
It supports I2S, Left-Justified (LJ), and Time-Division Multiplexed (TDM) output formats.