UDA1334TS/N1,118

Overview

The UDA1334TS is a low-power stereo digital-to-analog converter (DAC) manufactured by NXP Semiconductors. It integrates a digital filter, noise shaper, and Filter Stream DAC (FSDAC), eliminating the need for external analog post-filtering. The device supports I2S-bus and LSB-justified formats with word lengths up to 24 bits. It operates in slave mode only, requiring an external system clock. Key features include automatic system clock detection, digital de-emphasis at 44.1 kHz, and mute control. Power supply voltage ranges from 1.8 V to 3.6 V, with typical power dissipation of 7 mW at 2.0 V and 17 mW at 3.0 V.

Feature Summary

• Integrated digital filter and Filter Stream DAC (FSDAC) with no analog post-filtering required
• Supports I2S-bus and LSB-justified serial data formats (16, 20, or 24 bits)
• Automatic detection of system clock versus sample rate ratio
• Digital de-emphasis function for 44.1 kHz sampling rates and soft mute capability

Applications

• Portable MD players
• MP3 players
• DVD players

Procurement Notes

Verify that the design utilizes slave mode operation, as the UDA1334TS requires an external system clock and digital interface signals. Ensure all supply connections (VDDA and VDDD) are tied to the same external power supply unit. Confirm that input pads are compatible with the target logic voltage levels, noting that 5 V tolerance is supported only when the supply voltage is between 2.7 V and 3.6 V.

Selection Notes

Select this component for applications requiring high linearity and wide dynamic range without external reconstruction filters. The output voltage scales proportionally with the power supply voltage; therefore, design the analog front-end to accommodate the specific supply rail chosen (e.g., 0.5 V RMS at 2.0 V supply vs. 0.75 V RMS at 3.0 V supply). Consider the Sleep mode current consumption if battery life is critical.

Part Context

The UDA1334TS is part of the Philips/NXP audio DAC family designed for portable consumer electronics. It utilizes a semi-digital reconstruction filter technique where filter coefficients are implemented as current sources summed at a virtual ground. This architecture provides high signal-to-noise performance and low clock jitter sensitivity compared to traditional DAC architectures.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided documentation.

FAQ

How is the digital audio interface format selected?

The format is selected via the SFOR1 and SFOR0 pins. Low/Low selects I2S-bus; Low/High selects LSB-justified 16-bit; High/Low selects LSB-justified 20-bit; High/High selects LSB-justified 24-bit.

What is the function of the PCS pin?

The PCS pin is a 3-level input used for power control and sampling frequency selection. Low sets normal operating mode, Mid sets low sampling frequency mode (higher oversampling), and High activates Power-down or Sleep mode.

Does the UDA1334TS require an external analog post-filter?

No, the integrated Filter Stream DAC (FSDAC) has inherent filtering characteristics that eliminate the need for external analog post-filtering.