UDA1351H/N1,551

Overview

The UDA1351H is a single-chip IEC 958 audio decoder with an integrated stereo digital-to-analog converter (DAC) employing bitstream conversion techniques. It operates on a 2.7 V to 3.6 V supply and supports sampling frequencies from 28 kHz up to 100 kHz, including standard rates of 32, 44.1, 48, 64, 88.2, and 96 kHz. The device features an on-chip PLL for clock regeneration, a third-order noise shaper, and a Filter Stream DAC (FSDAC). Key electrical parameters include a typical signal-to-noise ratio of 100 dB at 48 kHz and 96 kHz, with total harmonic distortion plus noise of -85 dB at 0 dBFS. Power consumption is approximately 80 mW in playback mode at 48 kHz.

Feature Summary

• Integrated IEC 958 decoder with selectable dual channel input and on-chip amplifier for CMOS level conversion.
• Supports multiple digital interfaces: I2S-bus and LSB-justified formats (16, 20, 24 bits) for both data input and output.
• Includes an interpolating filter (fs to 128fs), third-order noise shaper, and FSDAC requiring no analog post-filtering.
• Controlled via static pins or L3 microcontroller interface for volume, bass/treble boost, de-emphasis, and mute functions.

Applications

• Digital audio systems requiring IEC 958 (SPDIF) decoding and DAC functionality.
• Multi-purpose audio decoders where external DSP integration is supported via digital data interfaces.
• Embedded audio solutions utilizing the L3 interface for flexible system control.

Procurement Notes

Verify component authenticity as this part may be discontinued or superseded by newer models. Confirm package integrity for the QFP44 variant, ensuring leads are undamaged. Check manufacturing date codes against current inventory requirements. Validate that the specific ordering suffix matches the required pin configuration and environmental compliance standards documented in the original specification.

Selection Notes

Select the UDA1351H when a combined IEC 958 decoder and stereo DAC is required in a single package. Ensure the application supports the 2.7 V to 3.6 V supply voltage range. Choose this component if the design necessitates an internal PLL for clock regeneration from SPDIF inputs. Verify that the QFP44 package dimensions fit the PCB layout constraints and that the L3 or static pin control method aligns with the host controller capabilities.

Part Context

The UDA1351H is fully pin and function compatible with the UDA1350AH. It belongs to a family of audio codecs designed for cost-effective multi-purpose applications. A related variant, the UDA1351TS, offers similar functionality in an SSOP28 package but lacks certain interface features. This component represents a solution for integrating SPDIF decoding directly into audio processing chains without separate decoder chips.

Replacement Considerations

The UDA1351H is fully pin and function compatible with the UDA1350AH. Designers should verify that any substitute maintains the same QFP44 package and L3 interface timing characteristics. Cross-reference with newer NXP audio codec families if discontinuation is confirmed, ensuring support for 96 kHz sampling and IEC 958 input remains intact.