UDA1351H/N1,557

Overview

The UDA1351H is a single-chip IEC 958 audio decoder with an integrated stereo digital-to-analog converter (DAC) employing bitstream conversion techniques. It operates on a 2.7 to 3.6 V power supply and supports sampling frequencies from 28 up to 100 kHz, including standard rates of 32, 44.1, 48, 64, 88.2, and 96 kHz. The device features an on-chip PLL for clock regeneration, a third-order noise shaper operating at 128fs, and a Filter Stream DAC (FSDAC). Key performance metrics include a signal-to-noise ratio of 95 dB (typical) and channel separation of 96 dB. It offers flexible control via static pins or an L3 microcontroller interface.

Feature Summary

• Integrated IEC 958 decoder with selectable dual-channel input and on-chip amplifier for CMOS level conversion.
• Supports multiple digital interfaces: I2S-bus and LSB-justified formats (16, 20, 24 bits) for both data input and output.
• Includes an interpolating filter (1fs to 128fs), third-order noise shaper, and FSDAC requiring no analog post-filtering.
• Features soft mute with cosine roll-off, automatic de-emphasis, and programmable volume/bass/treble controls via L3 interface.

Applications

• Digital audio systems
• IEC 958 compliant audio playback devices

Procurement Notes

Verify the package type QFP44 (SOT307-2) matches the design footprint. Confirm the specific suffix H/N,557 corresponds to the full-featured version described in the datasheet, distinct from the UDA1351TS SSOP28 variant which lacks certain interfaces. Ensure compatibility with the 2.7–3.6 V supply range required for both digital and analog sections.

Selection Notes

Select this component when an integrated solution for IEC 958 decoding and DAC conversion is required without external DSP processing for basic applications. It is suitable for designs needing master-mode clock generation (256fs output) or slave-mode synchronization. Consider the L3 interface if complex configuration like volume control or auto-mute bypass is needed; otherwise, static pin control suffices for simpler implementations.

Part Context

The UDA1351H is fully pin and function compatible with the UDA1350AH. It belongs to a family that includes the UDA1351TS, which is housed in an SSOP28 package and provides IEC 958 input to the DAC only. The UDA1351H is the full-featured version in a QFP44 package, offering additional digital input/output interfaces and comprehensive control options.

Replacement Considerations

The UDA1351H is directly compatible with the UDA1350AH due to identical pin and function mapping. Designers should verify that any replacement maintains the QFP44 package dimensions and electrical characteristics, particularly the 2.7–3.6 V supply range and IEC 958 decoding capabilities.

FAQ

How does the UDA1351H handle muting during lock loss?

By default, the DAC and data output interfaces are muted until the IC locks to the input signal. This is a hard mute performed in the SPDIF interface. In L3 mode, this auto-mute can be bypassed by setting the AutoMT bit to logic 0.

What is the purpose of the LOCK pin?

The LOCK pin indicates the status of the IEC 958 decoder and PLL. It asserts HIGH when both the decoder and PLL are locked and PCM data is detected. It goes LOW if the system is out-of-lock or if non-PCM data is detected while locked.

Can the UDA1351H operate without an external DSP?

Yes, in Mode 1, the UDA1351H processes IEC 958 input directly to the DAC using its internal audio feature processor, interpolator, and noise shaper, requiring no external digital signal processor.