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The UDA1352TS is a single-chip IEC 60958 audio decoder with an integrated stereo DAC employing bitstream conversion techniques. It operates from a 2.7 V to 3.6 V supply and supports sampling frequencies from 28 kHz up to 55 kHz, specifically targeting 32.0, 44.1, and 48.0 kHz standards. The device features a 20-bit data path in the interpolator and includes an on-chip PLL for clock regeneration. Key performance metrics at VDDA=3.0 V include a signal-to-noise ratio of 100 dB and channel separation of 110 dB. It provides independent left/right volume control, bass boost, and treble control via L3-bus or I2C-bus interfaces.
Verify package integrity upon receipt; the component uses an SSOP28 plastic shrink small outline package. Confirm that the SELSTATIC and SELIIC pins are correctly configured for the intended control interface before power-up. Ensure analog and digital grounds are properly separated according to the block diagram requirements to maintain signal integrity.
Select this component for applications requiring direct SPDIF decoding without external DSP. Compare against the UDA1352HL if a larger LQFP48 package or additional features are needed. Ensure the system design accommodates the 2.7 V to 3.6 V supply range and provides necessary pull-up resistors for I2C bus operation.
The UDA1352TS is part of the UDA135x series by NXP Semiconductors. It serves as the SSOP28 variant, while the UDA1352HL represents the full-featured version in an LQFP48 package. Both share core decoding and DAC functionalities but differ in package footprint and potentially available pin access for system integration.
Public confirmed substitute part numbers: None.