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The UDA1361TS is a stereo Analog-to-Digital Converter (ADC) utilizing bitstream conversion techniques, designed for low-voltage portable digital audio equipment. It supports sampling frequencies from 5 to 110 kHz with up to 24 significant bits of serial output. The device operates on a single 2.4 V to 3.6 V supply and features integrated high-pass filtering for DC offset cancellation. Key electrical parameters include a signal-to-noise ratio of 100 dB at 48 kHz and 96 kHz sampling rates, and channel separation exceeding 100 dB. It accommodates I2S-bus and MSB-justified formats in master or slave modes.
Verify the specific ordering suffix against the manufacturer's latest product status documentation. Historical records indicate variations in RoHS compliance and halogen-free status across different suffixes for this part number. Confirm current manufacturing availability as older versions may be discontinued. Ensure the package type matches the SSOP16 (SOT369-1) specification provided in the datasheet.
Select this component for applications requiring a dedicated stereo ADC with low power consumption and small footprint. The device requires an external crystal for clock generation in master mode. Input voltage levels must be managed using external resistors if signals exceed 1 V RMS, specifically utilizing a 12 kΩ series resistor for 2 V RMS inputs. Ensure the system clock frequency aligns with the supported multiples of the sampling rate.
The UDA1361TS belongs to the UDA13xx family of audio converters from NXP Semiconductors. It serves as a specialized Analog-to-Digital Converter, distinct from full codec chips that include DACs. The datasheet supersedes previous data from January 2001, indicating updates to specifications or packaging details while maintaining core functionality.
Publicly confirmed substitute part numbers are not available in the provided source material. Designers should consult NXP Semiconductors for current portfolio alternatives or verify compatibility with similar bitstream ADCs based on pinout and interface requirements.