WM8196SCDS/V

Overview

The WM8196SCDS/V is a 16-bit analogue front end and digitiser IC designed for CCD and CIS sensors. It processes signals at up to 12MSPS using three channels with Reset Level Clamping, Correlated Double Sampling, and programmable gain/offset. A single high-speed ADC time-multiplexes the outputs. The device operates on a 5V analog supply and supports 5V or 3.3V digital I/O. Typical power consumption is 300mW. Digital data is available in 8-bit or 4-bit multiplexed formats via a serial control interface.

Feature Summary

• 16-bit resolution with 12MSPS conversion rate
• Three processing channels featuring RLC, CDS, and PGA
• Supports 5V single or 5V/3.3V dual supply operation
• Internally generated voltage references and 4-bit DAC

Applications

• Flatbed and sheetfeed scanners
• USB compatible scanners
• Multi-function peripherals
• High-performance CCD sensor interfaces

Procurement Notes

Verify the 'V' suffix indicates the lead-free (Pb free) version in the 28-lead SSOP package. Confirm the operating temperature range is 0°C to 70°C and the Moisture Sensitivity Level is MSL3. Ensure the specific revision matches the required design specifications.

Selection Notes

Select this component for applications requiring simultaneous processing of RGB signals from CCD sensors. Verify that the input signal range fits within the 0.4V to 4.08Vp-p full-scale limit. Ensure the system can provide the necessary master clock frequency relative to the pixel sample rate.

Part Context

Manufactured by Wolfson Microelectronics plc (now Cirrus Logic), this device is part of the WM8196 family. It serves as an alternative to the WM8198 series for CIS/CCD applications. The SCDS/R variant denotes tape and reel packaging, while SCDS/V denotes tube packaging.

Replacement Considerations

Public confirmed substitute part numbers include WM8196SCDS-R and WM8196SCDS/R V. These variants share identical electrical characteristics but differ in packaging format or moisture sensitivity handling requirements.

FAQ

What is the maximum conversion rate?

The WM8196 supports a maximum conversion rate of 12 MSPS.

How is the reset level clamping controlled?

RLC is controlled by the RLC/ACYC pin or internal registers. It clamps the signal during the CCD reset period using an internal 4-bit DAC or an external reference.

What are the digital supply options?

The digital I/O supply (DVDD2) can operate at either 5V or 3.3V, while the digital core supply (DVDD1) must be 5V.