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The WM8741GEDS/V is a stereo digital-to-analogue converter (DAC) from Cirrus Logic, housed in a 28-lead SSOP package. It features a multi-bit sigma-delta architecture supporting PCM data word lengths of 16 to 32 bits and sampling rates up to 192 kHz. The device also handles DSD bit-stream formats for SACD applications. Electrical specifications include a typical SNR of 125 dB (A-weighted stereo at 48 kHz) and -100 dB THD. It operates with analogue supplies of 4.5 V to 5.5 V and digital supplies of 3.15 V to 3.6 V.
Verify the ordering suffix 'V' indicates the tape and reel packaging variant with a reel quantity of 2,000 units, distinct from the tube-packaged 'DS' version. Confirm the temperature range is -0°C to +70°C and that the component is lead-free. Check for any product change notices regarding pin compatibility with the WM8740.
Select this component when differential analogue voltage outputs are required. Ensure the system design accommodates separate analogue (AVDD) and digital (DVDD) supply rails within their specified ranges. Verify that the master clock frequency supports the desired sample rate, as MCLK must be established before audio data begins.
The WM8741GEDS/V is part of the WM8741 family, which is pin-compatible with the WM8740. It serves as a high-performance alternative for stereo DAC applications requiring low jitter tolerance and advanced digital filtering capabilities. The device integrates dithered digital interpolation filters and a switched capacitor multi-bit stage.
The WM8741 is pin-compatible with the WM8740. Designers replacing other components should verify if the target application requires the specific DSD support or filter characteristics unique to the WM8741 architecture.
The WM8741 supports standard PCM formats including right justified, left justified, I2S, and DSP serial port interfaces. It also supports DSD bit-streams in both direct and PCM-converted (DSD Plus) modes.
The WM8741 includes internal Power On Reset circuits for both analogue and digital sections. DVDD must be established before MCLK starts, and AVDD must be established before the device outputs signals to ensure proper initialization.
The maximum capacitance load for the differential analogue voltage outputs is 1 nF.