WM9713CLGEFL/V

Overview

The WM9713CLGEFL/V is a highly integrated AC'97 audio and touchpanel codec designed for mobile computing. It features stereo DACs with 94dB SNR and stereo ADCs with 87dB SNR, alongside an auxiliary mono DAC and a dedicated PCM voice DAC. The device includes on-chip headphone drivers (45mW) and speaker drivers (400mW). It supports resistive touchpanels with 12-bit resolution and integrates a PLL for clock generation from 2.048MHz to 78.6MHz inputs. Operating voltages range from 1.8V to 3.6V, housed in a 48-lead QFN package.

Feature Summary

• Dual CODEC architecture supporting hi-fi stereo via AC-Link and voice functions via PCM SSP.
• Integrated capacless headphone and speaker output drivers reducing external component count.
• Resistive touchpanel interface supporting 4-wire and 5-wire panels with pen-down detection.
• On-chip PLL generates audio clocks from input frequencies between 2.048MHz and 78.6MHz.

Applications

• Smartphones
• Personal Digital Assistants (PDA)
• Handheld and Tablet Computers

Procurement Notes

Verify the specific ordering suffix 'V' indicates tray packaging as per Cirrus Logic documentation. Confirm the temperature range is -25°C to +85°C and the package is a lead-free 48-lead QFN. Ensure compatibility with AC'97 Rev 2.2 standards for system integration.

Selection Notes

Select this component for applications requiring combined high-fidelity audio playback and resistive touch control in a single IC. Consider the power consumption profiles for different modes, such as low-power standby or active PCM voice calls, when designing battery-operated systems.

Part Context

The WM9713L serves as a pin-compatible upgrade to the WM9712, adding PCM voice codec capabilities. It consolidates audio processing, touch digitization, and wireless chipset interfaces into one package, simplifying board layout for portable devices.

Replacement Considerations

WM9713CLGEFL/RV is the tape-and-reel version of the same device. Verify if the packaging difference meets assembly requirements.

FAQ

What is the maximum input clock frequency supported by the internal PLL?

The PLL supports input clock frequencies ranging from 2.048MHz up to 78.6MHz.

Does the device support capacless headphone connections?

Yes, the device supports direct capacless connections to headphones, speakers, and earpieces to save board area.

What is the resolution of the integrated touchpanel ADC?

The touchpanel interface provides 12-bit resolution with an Integral Non-Linearity (INL) error of ±2 LSBs.