ZL40262LDG1

Overview

The ZL40262LDG1 is a two-output ultra-low additive phase noise fanout buffer designed for PCIe Gen 1 to 5 and UPI/QPI applications. It accepts any differential input format and provides two differential HCSL outputs. The device supports clock frequencies from 0 to 400 MHz and operates on 2.5V or 3.3V power supplies. Key electrical parameters include an ultra-low additive jitter of 32 fs (12kHz to 20MHz band at 400MHz), a maximum output-to-output skew of 50 ps, and an input-to-output delay of 1 ns. It features an embedded LDO for superior power supply noise rejection and individual output enable pins.

Feature Summary

• Ultra-low additive jitter: 32 fs in the 12kHz to 20MHz integration band at 400MHz clock frequency
• Supports clock frequencies from 0 to 400 MHz with one differential input accepting any format
• Two differential HCSL outputs with individual output enable pins for each pair
• Embedded Low Drop Out (LDO) voltage regulator providing superior power supply noise rejection

Applications

• PCI Express generation 1/2/3/4/5 clock distribution
• UPI/QPI clock distribution
• Low jitter clock trees
• Logic translation
• Clock and data signal restoration

Procurement Notes

Verify the ordering suffix against the datasheet: 'LDG1' indicates a 20-pin QFN package supplied in trays, while 'LDF1' denotes tape and reel packaging. Confirm that the required operating temperature range (-40°C to +85°C) aligns with system specifications. Ensure power supply decoupling capacitors are placed close to VDD and VDDO pins as recommended for optimal performance.

Selection Notes

Select this component when distributing low-jitter HCSL clocks to multiple destinations requiring PCIe Gen 1 through 5 compliance. It is suitable for systems needing logic translation between different clock domains or signal restoration. Verify that the input source can drive the specified differential or single-ended input requirements within the 0 to 400 MHz range.

Part Context

The ZL40262LDG1 belongs to the ZL40262 family of ultra-low additive jitter fanout buffers manufactured by Microchip Technology (formerly Microsemi). It is specifically engineered for high-speed serial interface clock distribution, offering transparent buffering without adding significant jitter to the source clock signal.

Replacement Considerations

Public confirmed substitute part numbers are not available in the provided documentation. Consult official Microchip resources for cross-reference information if alternative sourcing is required.

FAQ

How should unused outputs be handled?

Unused outputs should be left unconnected.

What is the maximum output-to-output skew?

The maximum output-to-output skew is 50 ps.

Can the device transfer spread-spectrum clocking signals?

Yes, the device transfers spread-spectrum signals without attenuation.