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74AUP1G00GN,132
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Product Detailed Parameters
- Description：IC GATE NAND
- Series：*
- Mfr：Nexperia USA Inc.
- Package：Bulk
- Logic Type：-
- Number of Circuits：-
- Number of Inputs：-
- Features：-
- Voltage - Supply：-
- Current - Quiescent (Max)：-
- Current - Output High, Low：-
- Input Logic Level - Low：-
- Input Logic Level - High：-
- Max Propagation Delay @ V, Max CL：-
- Operating Temperature：-
- Mounting Type：-
- Supplier Device Package：-
- Package / Case：-
- Grade：-
- Qualification：-
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Overview
The 74AUP1G00GN,132 is a single 2-input NAND gate from the Nexperia AUP series. It operates within a supply voltage range of 0.8 V to 3.6 V and features Schmitt-trigger inputs for noise tolerance. The device includes I_OFF circuitry to prevent backflow current during partial power-down. It supports operating temperatures from -40 °C to +125 °C and complies with JEDEC standards for various voltage levels.
Feature Summary
- Schmitt-trigger action at all inputs ensures tolerance for slower input rise and fall times.
- I_OFF circuitry disables the output to prevent damaging backflow current when powered down.
- Low static power consumption with maximum ICC of 0.9 μA across the entire VCC range.
Applications
- Partial power-down applications requiring backflow protection
- Systems with slow-changing input signals needing noise immunity
- Low-power digital logic designs in portable electronics
Procurement Notes
Verify the specific suffix GN indicates the XSON-6 (SOT1115) package configuration. Confirm the 132 tape-and-reel packaging format matches assembly requirements. Ensure the component meets the required temperature grade and JEDEC compliance standards for the target application environment.
Selection Notes
Select this component for applications requiring low power dissipation and high noise immunity. The Schmitt-trigger inputs are suitable for noisy environments or slow signal transitions. Verify that the 0.8 V to 3.6 V supply range aligns with the system's voltage rails and that the XSON-6 package fits the PCB layout constraints.
Part Context
This part belongs to the 74AUP1G00 family of low-power 2-input NAND gates. It shares functional characteristics with other variants like 74AUP1G00GM but differs in package type. The AUP series is designed for ultra-low power and high-speed performance in modern CMOS applications.
Replacement Considerations
Direct substitutes include 74AUP1G00GM,132 and 74AUP1G00GS,132, which offer identical logical functions but utilize different packages such as XSON-6 (SOT886) or XSON-6 (SOT1202). Verify pinout compatibility and thermal performance before substitution.
FAQ
What is the purpose of the I_OFF circuitry in this device?
The I_OFF circuitry disables the output to prevent damaging backflow current through the device when it is in a partial power-down state.
Does this gate support slow input signal transitions?
Yes, the Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times.
