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The Nexperia 74AUP1G373GF,132 is a single D-type transparent latch with 3-state outputs. It operates within a supply voltage range of 0.8 V to 3.6 V and features Schmitt-trigger inputs for noise immunity. The device includes IOFF circuitry to prevent backflow current during partial power-down. Static supply current is limited to 0.9 μA maximum at 25 °C. Propagation delay from data input (D) to output (Q) ranges from 1.5 ns to 4.5 ns depending on voltage and load capacitance.
Verify the ordering suffix GF corresponds to the XSON6 package SOT1202 as defined in the official datasheet. Confirm that the specific revision level matches design requirements. Check RoHS compliance status and REACH declarations against current regulatory standards before finalizing procurement specifications.
Select this component when a single latch with high-impedance states is required. Ensure the system voltage falls within the 0.8 V to 3.6 V range. Consider the small XSON6 footprint if board space is constrained. Verify that the Schmitt-trigger input characteristics meet the signal integrity requirements of the driving source.
This part belongs to the 74AUP series of advanced ultra-low power CMOS logic devices. The series is designed for applications requiring minimal power consumption across a wide voltage spectrum. The 74AUP1G373 variant specifically provides latching functionality with three-state control, distinguishing it from standard buffers or non-latched gates within the same family.
Direct replacements include other 74AUP1G373 variants with different packages such as GM (SOT886) or GN (SOT1115). Cross-referencing pinouts is essential when substituting packages. Ensure any alternative maintains the same 3-state logic function and voltage compatibility.