74AUP1G373GM,115

Overview

The Nexperia 74AUP1G373GM,115 is a single D-type transparent latch with 3-state outputs. It operates within a supply voltage range of 0.8 V to 3.6 V and features Schmitt-trigger inputs for noise tolerance. The device includes IOFF circuitry to prevent backflow current during partial power-down. It is housed in an XSON6 (SOT886) package with dimensions of 1 x 1.45 x 0.5 mm. Static supply current is limited to 0.9 μA maximum at 25 °C. Propagation delay from data input to output ranges from 1.5 ns to 4.9 ns depending on load capacitance and temperature.

Feature Summary

• Schmitt-trigger action at all inputs provides tolerance for slower rise and fall times.
• IOFF circuitry disables outputs to prevent damaging backflow current when powered down.
• High noise immunity with low static and dynamic power consumption across the full voltage range.
• ESD protection exceeds 5000 V for Human Body Model and 1000 V for Charged Device Model.

Applications

• Partial power-down applications requiring isolation of powered-down sections
• Data storage and buffering in low-voltage digital systems
• Level shifting between different voltage domains

Procurement Notes

Verify the specific ordering suffix GM corresponds to the XSON6 SOT886 package configuration required for your design. Confirm that the component status remains active as production availability may change. Ensure compliance with RoHS and REACH regulations by checking the latest environmental documentation provided by the manufacturer before finalizing procurement specifications.

Selection Notes

Select this component when a single latch with three-state control is needed in space-constrained designs. The XSON6 package offers a compact footprint suitable for high-density PCB layouts. Consider the wide operating temperature range and low power dissipation characteristics for battery-powered or thermally sensitive applications requiring reliable data retention.

Part Context

This part belongs to the 74AUP series of advanced ultra-low-power CMOS logic devices. The AUP family is designed for applications requiring operation at supply voltages below 3.3 V while maintaining high speed. The 74AUP1G373 specifically provides transparent latch functionality with output enable control, distinguishing it from standard flip-flops or non-latching buffers within the same logic family.

Replacement Considerations

Check for pin-compatible alternatives such as the 74AUP1G373GW or 74AUP1G373GN if different package styles are preferred. Verify functional equivalence regarding propagation delays and electrical characteristics against other single D-type latches in the market before substitution.