74AUP1G74GD,125

Overview

The Nexperia 74AUP1G74GD,125 is a single D-type flip-flop with positive-edge triggering and complementary outputs. It operates within a supply voltage range of 0.8 V to 3.6 V, ensuring low static power consumption of 0.9 μA maximum. The device features Schmitt-trigger inputs for noise tolerance and IOFF circuitry for partial power-down protection. It is housed in an SOT-363 (SC-88) package and supports operating temperatures from -40°C to +125°C.

Feature Summary

• Positive-edge triggered D-type flip-flop with complementary outputs
• IOFF circuitry prevents backflow current during partial power-down
• Schmitt-trigger inputs provide high noise immunity
• Wide supply voltage range supporting multiple JEDEC standards

Applications

• Parallel data storage applications
• Shift register construction
• Timing delay circuits
• Data acquisition systems

Procurement Notes

Verify the specific suffix GD corresponds to the SC-88/SOT-363 package variant when sourcing. Confirm AEC-Q100 automotive qualification status if required for your application, as standard commercial variants may differ. Ensure compatibility with your PCB footprint for the specified surface-mount package before finalizing procurement orders.

Selection Notes

Select this component for designs requiring minimal board space and low power consumption at sub-1V logic levels. The integrated IOFF feature is critical for battery-powered systems requiring partial power-down modes. Verify input voltage levels against the 0.8V to 3.6V range to ensure proper logic threshold compliance across all operating conditions.

Part Context

This part belongs to the Nexperia 74AUP1G series of ultra-low power CMOS logic devices. The AUP family is optimized for applications requiring operation down to 0.8V while maintaining high speed. The 74AUP1G74 specifically implements a single D-flip-flop function, distinguishing it from buffer or gate-based members of the same logical family.

Replacement Considerations

• 74AUP1G74GW,125
• 74AUP1G74GM,125

FAQ

Does the 74AUP1G74GD support partial power-down?

Yes, the device includes IOFF circuitry that disables the output to prevent damaging backflow currents when the device is powered down.

What is the minimum operating voltage for this flip-flop?

The minimum supply voltage (VCC) for the 74AUP1G74GD is 0.8 V.