859S1601BGILF

Overview

The ICS859S1601I is a 16:1 LVCMOS/LVTTL-to-LVPECL/LVDS clock multiplexer from the HiPerClockS family. It accepts sixteen selectable single-ended clock inputs and provides one differential output pair configurable as LVPECL or LVDS via the SEL_OUT pin. The device operates up to 250MHz with a typical propagation delay of 1.0ns. It supports full 3.3V or 2.5V supply modes, features internal pull-downs on select pins, and includes an active-high output enable (OE) pin. Additive phase jitter is typically 0.20ps RMS at 155.52MHz.

Feature Summary

• 16:1 Multiplexing: Selects one of sixteen LVCMOS/LVTTL inputs for a single differential output.
• Configurable Output Levels: Supports both LVPECL and LVDS output standards via the SEL_OUT control pin.
• High Speed Performance: Maximum output frequency of 250MHz with typical propagation delay of 1.0ns.
• Flexible Power Supply: Operates in either 3.3V or 2.5V supply configurations.

Applications

• Clock distribution circuits requiring selection among multiple source clocks.
• Systems utilizing differential signaling standards such as LVPECL or LVDS.
• High-performance timing solutions within the HiPerClockS ecosystem.

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current documentation. Suffixes such as 'LF' indicate lead-free/RoHS compliance, while 'T' denotes tape and reel packaging. Confirm that the required package type (Tube vs. Reel) matches the production needs. Ensure the voltage domain (3.3V or 2.5V) aligns with the system design before procurement.

Selection Notes

Select this component when a 16:1 multiplexer interface between single-ended CMOS/TTL sources and differential LVPECL/LVDS loads is required. Choose based on the target supply voltage; note that LVDS operation requires floating VCC_TAP at 3.3V but connects it to VCC at 2.5V. Verify that the input clock frequencies do not exceed the 250MHz maximum rating and that the thermal environment supports the specified junction temperature limits.

Part Context

The ICS859S1601I belongs to the IDT HiPerClockS family of high-performance clock solutions. It is manufactured by Integrated Device Technology (IDT), which was subsequently acquired by Renesas Electronics Corporation. The device is housed in a 28-lead TSSOP package with dimensions of 4.4mm x 9.7mm.

Replacement Considerations

Publicly confirmed substitute part numbers are not available in the provided datasheet. Designers should consult the manufacturer for cross-reference information regarding newer generations or alternative multiplexers within the HiPerClockS portfolio.

FAQ

How is the output level selected between LVPECL and LVDS?

The output level is controlled by the SEL_OUT pin. Driving SEL_OUT HIGH selects LVPECL levels, while driving it LOW selects LVDS levels.

What is the function of the VCC_TAP pin?

VCC_TAP is a power supply pin. For LVPECL operation, it connects to VCC. For LVDS operation at 3.3V, it must be left floating; at 2.5V, it connects to VCC.

How does the device handle unused clock inputs?

Unused CLK inputs can be left floating. For additional protection, a 1kΩ resistor may be tied from the input to ground, though this is not strictly required due to internal pulldowns.