8T49N240-028NLGI

Overview

The 8T49N240-028NLGI is an ultra-performance jitter attenuator manufactured by Renesas Electronics. It utilizes FemtoClock NG PLL technology to provide low RMS phase jitter performance, with typical values of 225fs at 156.25MHz (12KHz to 20MHz) from Output Divider A and 219fs from Output Divider B. The device supports four LVPECL or LVDS outputs and accepts differential input levels including LVPECL, LVDS, and HCSL. It operates on a single 2.5V or 3.3V power supply and features an I2C programming interface for register configuration.

Feature Summary

• Fourth-generation FemtoClock NG PLL technology
• Four selectable LVPECL or LVDS outputs
• RMS phase jitter: 225fs typ (156.25MHz, 12KHz-20MHz)
• I2C programmable interface

Applications

• PCI Express Gen2 (5Gb/s) compliant systems
• PCI Express Gen3 (8Gb/s) compliant systems
• High-speed data communication equipment

Procurement Notes

Verify the specific suffix '028NLGI' against official Renesas documentation to confirm factory pre-programmed frequency configurations. Ensure compatibility with the required 2.5V or 3.3V supply voltage and check for RoHS compliance status in the latest datasheet revision before procurement.

Selection Notes

Select this component when low jitter attenuation is required for PCI Express Gen2 or Gen3 applications. Confirm that the four output channels meet the system's LVPECL or LVDS requirements. Verify that the internal crystal oscillator or external reference clock inputs align with the target design frequencies.

Part Context

This part belongs to the 8T49N240 series of clock synthesizers. It is designed as a low RMS phase jitter solution capable of accepting either an internal crystal oscillator or external clock references. The device allows up to three different output frequencies to be selected from various internal dividers and oscillators.

FAQ

What is the VCO range for the 8T49N240?

The FemtoClock NG VCO range for the 8T49N240 is 1.92GHz to 2.5GHz.

Can the 8T49N240 accept HCSL input signals?

Yes, the CLK and nCLK input pair can accept differential input levels including LVPECL, LVDS, and HCSL.

How are output frequencies configured after power-up?

After power-up, two frequency select pins determine one of up to four different sets of factory preprogrammed configurations. These settings can be overwritten via the I2C interface.