9EPRS475BGLF

Overview

The ICS9EPRS475 is a main clock synthesizer designed for AMD embedded systems, including M690T/780E platforms. It provides multiple low-power differential outputs: two Greyhound-compatible K8 CPU pairs, four SRC pairs, two SouthBridge SRC pairs, and three ATIG pairs. It includes one selectable 100MHz differential or 66MHz single-ended HTT clock, two 48MHz USB clocks, and three 14.318MHz reference clocks. The device operates on a nominal 3.3V supply in a 56-pin TSSOP package.

Feature Summary

• Supports Spread Spectrum for EMI reduction across CPU, HTT, SRC, SB_SRC, and ATIG outputs.
• Outputs are individually controllable via SMBus interface.
• CPU outputs feature cycle-to-cycle jitter less than 150ps; SRC and ATIG outputs have jitter under 125ps.
• Frequency accuracy is maintained at +/- 300ppm for CPU, SRC, and ATIG clocks.

Applications

• AMD M690T system designs
• AMD 780E system designs
• Embedded AMD-based computer systems

Procurement Notes

Verify the manufacturer designation as Integrated Circuit Systems, Inc. (ICS) or IDT, as Renesas branding may appear in distributor listings. Confirm the specific suffix 'BGLF' corresponds to the 56-pin TSSOP package and RoHS compliance status using the official datasheet.

Selection Notes

Select this component when designing for AMD embedded architectures requiring synchronized multi-output clocking. Ensure the design supports the required 3.3V power rails and utilizes an external crystal for the 14.318MHz reference input.

Part Context

This device belongs to the ICS9EPRS series of clock synthesizers. It serves as a central timing solution for motherboard chipsets, replacing discrete oscillator solutions with a programmable, multi-output integrated circuit.

Replacement Considerations

Consult the official ICS/IDT documentation for direct pin-compatible replacements within the same family. Verify that any substitute maintains the specific Greyhound and LPRS output characteristics required by the target AMD chipset.

FAQ

How is the HyperTransport clock frequency selected?

The HTT clock frequency is selected via the SEL_HTT66 pin. A logic high selects a 66MHz single-ended clock, while a logic low selects a 100MHz differential clock.

What is the function of the RESTORE# pin?

RESTORE# is an open-drain I/O. As an input, it restores the PLLs to their power-up default state upon a falling edge trigger. As an output, it indicates when the internal watchdog timer expires.

Does the device require external resistors for the LPRS outputs?

No, the LPRS (Low Power Reduced Swing) outputs do not require 50-ohm shunt resistors to ground or 33-ohm series resistors.