A3PE600-PQ208

Overview

The A3PE600-PQ208 is a ProASIC3E Flash FPGA featuring 600,000 system gates and 13,824 VersaTiles. It utilizes a 130-nm flash-based CMOS process for nonvolatile configuration. The device supports a maximum system performance of 350 MHz and includes 108 kbits of True Dual-Port SRAM organized into 24 blocks. It offers up to 270 user I/Os within a PQFP-208 package (28 x 28 mm). Key features include Instant On Level 0 support, bank-selectable I/O voltages (1.5 V, 1.8 V, 2.5 V, 3.3 V), six Clock Conditioning Circuits with integrated PLLs, and on-chip AES decryption for secure in-system programming.

Feature Summary

• Nonvolatile flash technology enables instant-on operation without external boot PROMs and immunity to firm errors from high-energy neutrons.
• Integrated security mechanisms including FlashLock and 128-bit AES decryption protect intellectual property during in-system programming.
• Flexible I/O structure supports mixed-voltage operation across eight banks with programmable slew rates and drive strengths.
• Advanced clock conditioning circuits provide configurable phase-shift, multiply/divide capabilities, and low-jitter global clock distribution.

Applications

• Secure remote field updates over public networks
• Consumer electronics requiring instant-on functionality
• Networking and communications equipment
• Avionics systems

Procurement Notes

Verify the specific ordering suffix against the manufacturer's current datasheet to confirm temperature grade and packaging compliance. Ensure the component matches the required speed grade and that any necessary software licenses for ARM cores or encryption are accounted for during procurement planning.

Selection Notes

Select this device for designs requiring nonvolatile configuration and high-density logic within a QFP package. Consider the PQ208 pin count limits when mapping I/O standards. Verify that the 108 kbits of embedded SRAM meets memory requirements before choosing higher-density alternatives like the A3PE1500.

Part Context

This component belongs to the Microsemi ProASIC3E family, which bridges the gap between ASIC costs and FPGA flexibility. It serves as a drop-in replacement for complex CPLDs and offers lower power consumption than SRAM-based FPGAs while retaining design data without battery backup.

Replacement Considerations

Pin-compatible options within the ProASIC3E family include the A3PE1500 and A3PE3000. These devices offer higher gate counts but require verification of routing resource availability and I/O standard limitations specific to the PQ208 package.

FAQ

Does the A3PE600-PQ208 require an external configuration PROM?

No, the device uses reprogrammable flash technology, allowing it to be Instant On without external boot PROMs or microcontrollers.

How many Clock Conditioning Circuits (CCCs) are available in the PQ208 package?

The PQ208 package supports six CCC blocks, though only the center east and west PLLs are fully accessible for user I/O optimization; all six blocks remain usable for clock delay operations.

What security features are included for in-system programming?

The device includes FlashLock for design protection and an on-chip 128-bit AES decryption engine compliant with IEEE 1532 for secure ISP via JTAG.