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The AD73311LARUZ is a single-channel analog front-end processor from Analog Devices, integrating a 16-bit ADC and a 16-bit DAC. It operates on a single +3 V supply with power consumption of 33 mW maximum at 2.7 V. The device supports programmable sampling rates up to 64 kS/s and features a flexible serial interface for DSP connectivity. Key performance metrics include 76 dB SNR for the ADC and 77 dB SNR for the DAC within voiceband frequencies. It includes an on-chip reference, programmable gain amplifiers, and digital filters, housed in a 20-lead TSSOP package.
Verify the specific suffix 'RU' corresponds to the TSSOP-20 package option when sourcing. Confirm the industrial temperature range (-40°C to +105°C) matches system requirements. Check current availability status as distribution may vary. Ensure ESD precautions are observed during handling due to the sensitivity of the CMOS technology.
Select this component for applications requiring low group delay, specifically 25 µs for the ADC channel at 64 kHz. Consider the external digital filtering capabilities if further bandwidth reduction or SNR improvement is needed beyond the internal decimation filter. Verify that the host DSP can support the required serial clock timing and frame sync configurations for the SPORT interface.
The AD73311L is part of Analog Devices' general-purpose analog front-end family designed for speech and telephony applications. The 'ARU' suffix indicates the specific package variant (TSSOP) and temperature grade. This model serves as a complete solution for converting analog voice signals to digital data and vice versa without requiring external amplifiers or references.
Publicly confirmed substitute part numbers are not available in the provided documentation. Designers should consult Analog Devices for current pin-compatible or functionally equivalent alternatives if this specific package or revision is discontinued.
The device supports a maximum sample rate of 64 kS/s, determined by the internal master clock divider settings.
The on-chip reference provides a nominal 1.2 V output. A 0.1 µF capacitor must be connected between the REFCAP pin and AGND2 to stabilize the reference voltage.
The typical group delay for the ADC channel is 25 µs when operating at a 64 kHz output sample rate.