AD7730LBR

Overview

The AD7730L is a bridge transducer analog front end featuring a 24-bit sigma-delta ADC with no missing codes. It includes a two-channel programmable gain front end and a buffered differential input stage. The device supports unipolar ranges of 0 mV to +10/20/40/80 mV and bipolar ranges of ±10/20/40/80 mV. Key static performance metrics include an offset drift of 5 nV/°C, gain drift of 2 ppm/°C, and line frequency rejection exceeding 150 dB. It operates from a single +5 V supply and accepts reference voltages between 1 V and 5 V.

Feature Summary

• 230,000 counts peak-to-peak resolution with 24-bit no missing codes
• Two-channel programmable gain front end with buffered differential inputs
• On-chip 6-bit DAC for offset and tare removal
• FASTStep mode for rapid settling on step changes

Applications

• Weigh scales
• Pressure measurement

Procurement Notes

Verify the specific suffix 'LBR' against official documentation to confirm package type (SOIC or TSSOP) and temperature range (Industrial -40°C to +85°C). Ensure the master clock frequency matches the L variant specification of 2.4576 MHz rather than the standard AD7730 4.9152 MHz requirement.

Selection Notes

Select this component when high precision bridge sensor interfacing is required with low drift characteristics. The AD7730L is distinguished by its lower master clock frequency requirement compared to the standard AD7730. Verify that the application can accommodate the single +5 V analog supply and appropriate digital logic levels.

Part Context

The AD7730L is a variant of the AD7730 bridge transducer ADC family. While functionally similar, the AD7730L is specified for a master clock input frequency of 2.4576 MHz, whereas the standard AD7730 requires 4.9152 MHz. Both share the same core architecture and pinout.

Replacement Considerations

The standard AD7730 is a functional substitute but requires a 4.9152 MHz master clock instead of the 2.4576 MHz required by the AD7730L. Verify clock source compatibility before substitution.