AD807A-155BR

Overview

The AD807A-155BR is a fiber optic receiver integrating data quantization, signal level detection, clock recovery, and data retiming for 155 Mbps NRZ signals. It meets CCITT G.958 STM-1 Type A and Bellcore OC-3 requirements. The device features a phase-locked loop with a nominal center frequency of 155.52 MHz and output jitter of 2.0 degrees RMS. It operates from a single +5 V or –5.2 V supply, consuming 170 mW.

Feature Summary

• Integrated PLL-based clock recovery and data retiming without external crystals
• High-speed quantizer with 2 mV sensitivity and adjustable level detect threshold
• Patented phase detector architecture virtually eliminates pattern jitter
• Compliant with SONET OC-3 and SDH STM-1 regenerator standards

Applications

• SONET OC-3 fiber optic receivers
• SDH STM-1 fiber optic receivers
• STM-1 Type A regenerators
• OC-3 compliant optical network interfaces

Procurement Notes

Verify the specific suffix BR indicates the 16-lead narrow SOIC package option R-16A. Confirm the temperature range corresponds to the commercial grade specification of -40 °C to +85 °C. Ensure the ordering part number matches the required reel quantity if bulk packaging is needed rather than tube shipping.

Selection Notes

Select this component when designing 155 Mbps optical links requiring integrated clock recovery and retiming. The device simplifies design by eliminating external SAW filters or crystals. Consider the user-programmable damping factor capacitor for adjusting acquisition time versus jitter transfer peaking based on system stability requirements.

Part Context

This part belongs to the AD807 family of high-speed fiber optic receivers manufactured by Analog Devices. It is designed to work in conjunction with transimpedance amplifiers like the AD8015 to form complete low-cost receiver front ends. The device utilizes Extra Fast Complementary Bipolar (XFCB) technology for high performance.

Replacement Considerations

Public documentation lists the AD807A-155BRRL as an alternative reel version of the same functional device. Verify pin compatibility and electrical specifications against current datasheets before substitution. No other cross-manufacturer equivalents are confirmed in the provided source material.

FAQ

How is the PLL damping factor configured?

The damping factor is set by a single external capacitor connected between pins CF1 and CF2. A value of 0.15 µF provides a damping ratio of 5 at 155 MHz.

Does the device require a preamble for lock acquisition?

No, the frequency acquisition control loop acquires lock on random or scrambled data without requiring a preamble.

What is the maximum input signal level for the quantizer?

The input voltage range is specified from 2.5 V below VCC to VCC. The input overdrive is guaranteed up to 2.5 V while maintaining a bit error rate of ≤ 1 × 10⁻¹⁰.