AD808-622BR

Overview

The AD808-622BR is a fiber optic receiver with quantizer, clock recovery, and data retiming for 622 Mbps NRZ data. It meets CCITT G.958 STM-4 Type A and Bellcore OC-12 requirements. Key electrical parameters include a nominal center frequency of 622.08 MHz, capture range of 620–624 MHz, and tracking range of 620–624 MHz. Output jitter is typically 2.5 degrees RMS. The device operates from a single +5 V or –5.2 V supply, consuming 400 mW. Quantizer sensitivity is 4 mV typical, with an input resistance of 10 kΩ and capacitance of 2 pF.

Feature Summary

• Integrated PLL-based clock recovery and data retiming without requiring external crystals or SAW filters.
• Factory-trimmed VCO center frequency ensures reliable frequency acquisition on random or scrambled data without preamble.
• Patented phase detector architecture virtually eliminates pattern jitter throughout the device operation.
• Programmable signal level detect threshold with electrical hysteresis to prevent output chatter.

Applications

• SONET OC-12 fiber optic receivers
• SDH STM-4 regenerator systems
• High-speed optical communication front ends
• Telecommunications network interface units

Procurement Notes

Verify that the component matches the specific AD808-622BR variant, as Rochester Electronics distributes recovered parts. Confirm the package is the 16-lead narrow SOIC (R-16A) and check the temperature range rating of -40°C to +85°C. Ensure the ordering suffix corresponds to the desired reel or tube configuration if applicable, though standard retail units are typically in tubes. Cross-reference the manufacturer's lot code against current quality assurance standards.

Selection Notes

Select this component when designing SONET OC-12 or SDH STM-4 compliant optical links requiring integrated clock recovery. It is suitable for applications needing low jitter performance without external timing components. Consider the single-supply operation and low power consumption for portable or dense telecom equipment. Ensure the design accommodates the required damping capacitor for loop stability and the programmable threshold resistor for signal detection.

Part Context

The AD808 is part of Analog Devices' high-speed fiber optic receiver portfolio. It combines analog quantization with digital retiming functions. The BR suffix indicates the 16-lead narrow SOIC package option. This device simplifies system design by integrating the PLL and quantizer into a single monolithic circuit, reducing board space compared to discrete solutions.

Replacement Considerations

Publicly confirmed substitutes are not available in the provided documentation. Verify compatibility with existing PCB footprints and pin assignments if considering alternative manufacturers. Check if other AD808 variants meet the specific frequency and packaging requirements.

FAQ

Does the AD808 require an external crystal for clock recovery?

No, the AD808 uses a factory-trimmed VCO and a frequency acquisition control loop that allows it to acquire lock on random or scrambled data without a preamble or external crystal.

How is the jitter peaking of the PLL controlled?

Jitter peaking is controlled by the damping factor capacitor (CD) connected between pins CF1 and CF2. Using a 0.47 μF capacitor provides less than 0.1 dB of jitter peaking.

What is the purpose of the SDOUT pin?

The SDOUT pin provides a signal detect output that indicates whether the input signal amplitude is above or below a user-adjustable threshold, helping to manage loss of signal conditions.