AD808-622BRZRL7

Overview

The AD808-622BRZRL7 is a fiber optic receiver with quantizer, clock recovery, and data retiming for 622 Mbps NRZ data. It meets CCITT G.958 STM-4 Type A and Bellcore OC-12 requirements. The device features a phase-locked loop type clock recovery without a crystal, output jitter of 2.5 degrees RMS, and quantizer sensitivity of 4 mV. It operates from a single +5 V or -5.2 V supply, consuming 400 mW. The nominal center frequency is 622.08 MHz with a capture range of 620 to 624 MHz.

Feature Summary

• Integrated fiber optic receiver providing data quantization, signal level detection, clock recovery, and data retiming for 622 Mbps NRZ signals.
• PLL-based clock recovery architecture eliminates the need for external crystals or SAW filters using a patented frequency acquisition control loop.
• Low jitter performance of 2.5 degrees RMS achieved through fully differential signal architecture and dielectrically isolated process technology.
• Programmable level detect range allows user adjustment via a single external resistor, with electrical hysteresis to prevent signal chatter.

Applications

• SONET OC-12 fiber optic receivers
• SDH STM-4 regenerator systems
• High-speed optical communication front ends

Procurement Notes

Verify the specific ordering suffix matches the required packaging format, as the BRZRL7 designation indicates reel packaging. Confirm that the component meets all relevant environmental standards and RoHS compliance requirements for the intended deployment region. Ensure that the supply voltage and power dissipation characteristics align with the system's thermal management capabilities.

Selection Notes

Select this component for applications requiring integrated clock recovery and data retiming at 622 Mbps without external timing components. Consider the single-supply operation and low power consumption when designing power architectures. Evaluate the programmable threshold and damping factor capacitor options to optimize jitter transfer and acquisition time for specific network conditions.

Part Context

This part belongs to the AD808 family of high-speed fiber optic receivers manufactured by Analog Devices. It is designed to replace discrete solutions by integrating the quantizer, PLL, and retiming circuits into a single 16-lead SOIC package. The device supports both single-ended and differential input configurations when paired with appropriate preamplifiers.

Replacement Considerations

Direct replacements must support 622 Mbps NRZ data rates and meet similar jitter tolerance specifications. Verify pin compatibility and power supply requirements if substituting with other ADI receivers. Ensure that any alternative component provides comparable signal detect functionality and does not require additional external crystals for clock recovery.

FAQ

Does the AD808 require an external crystal for clock recovery?

No, the AD808 uses a phase-locked loop type clock recovery with a factory-trimmed VCO and a frequency acquisition control loop, eliminating the need for an external crystal or SAW filter.

How is the signal level detect threshold adjusted?

The level detect threshold is programmable via a single external resistor connected to the THRADJ pin, allowing a range from approximately 10 mV to 40 mV.

What is the typical output jitter of the device?

The typical output jitter is 2.5 degrees RMS, measured with a 2^7-1 PRN sequence, resulting from the fully differential signal architecture and low noise design techniques.